Address Sequence Generator for Memory BIST

International Journal of Computer Science and Engineering
© 2019 by SSRG - IJCSE Journal
Volume 6 Issue 11
Year of Publication : 2019
Authors : Mikalai Shauchenka
: 10.14445/23488387/IJCSE-V6I11P112

pdf
Citation:
MLA Style:

Mikalai Shauchenka, "Address Sequence Generator for Memory BIST" SSRG International Journal of Computer Science and Engineering 6.11 (2019): 55-59.

APA Style:

Mikalai Shauchenka,(2019). Address Sequence Generator for Memory BIST. SSRG International Journal of Computer Science and Engineering 6(11), 55-59.

Abstract:

In this work a structure that generates memory address sequences for built-in memory self tests is proposed. The idea is to significantly expand the set of address sequences. The structure consists of three components, namely the base address sequence generator, a device for generating and storing a matrix of binary vectors, and a device to calculate the address values. The idea behind this structure is to significantly expand the set ofdifferent address sequences including the standard well known and extensively used sequences for memory testing.

References:

[1] International Technology Roadmap for Semiconductors, Test and Test Equipment, 2015.
[2] Bushnell, M. L. Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits / M.L. Bushnell, V.D. Agrawal. – New York : Kluwer Academic Publishers, 2000. – 690 p.
[3] Goor, A.J. Optimizing memory BIST Address Generator implementations / A.J. Goor, H. Kukner, S. Hamdioui // Proc. of 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Athens, Greece. – 2011. – P. 572–576.
[4] Marinissen, E.J. Challenges in Embedded Memory Design and Test / E.J. Marinissen, B. Prince, D. Keitel-Schulz, Y. Zorian // Proc. of Design, Automation and Test in Europe Conference and Exhibition, Munich, Germany. – 2005. – P. 722–727.
[5] Aswin, A.M. Implementation and Validation of Memory Built in Self-Test (MBIST) –Survey / A.M. Aswin, S.S. Ganesh // International Journal of Mechanical Engineering and Technology (IJMET). – 2019. – Vol. 10, № 3. – P. 153–160.
[6] Golomb, S.W. Shift Register Sequences / S.W. Golomb.  San Francisco : Holden-Day, Inc., 1967.  224 p.
[7] Yarmolik, V.N. Generation and application of pseudorandom sequences for random testing / V.N. Yarmolik, S.N. Demidenko. – New York,NY,USA:John Wiley & Sons, Inc., 1988. – 167 c.
[8] Mohan, M. Review on LFSR for Low Power BIST / M. Mohan, S.S.A. Pillai // Proceedings of 3rd International Conference on Computing Methodologies and Communication (ICCMC), Erode, India.  2019.  P. 788-454.
[9] Hellebrand, S. A mixed mode BIST scheme based on reseeding of folding counters / S. Hellebrand, H.G. Liang,HJ. Wunderlich // Journal of Electronic Testing. – 2001. –№17. – P. –341–349.
[10] Ren,H. A Multi-polynomial LFSR Based BIST Pattern Generator for Pseudorandom Testing / H. Ren Z.Xiong// Proceedings of 2nd International Conference on Information Science and Control Engineering, Shanghai, China. – 2015. – P. 788-454.
[11] 15. Vennelakanti, S. Design and Analysis of Low Power Memory Built in Self-Test Architecture for SoC based Design / S. Vennelakanti, S. Saravanan // Indian Journal of Science and Technology. – 2015. – Vol 8, №14. – P. 1–5.
[12] Ajane, A. Comparison of binary and LFSR counters and efficient LFSR decoding algorithm / A. Ajane, P.M. Furth, E.E. Johnson // Proceedings IEEE 54th International Midwest Symposium Circuits Systems (MWSCAS), Seoul, Korea. – 2011. – P. 1–4.
[13] Morrison, D. Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications / D. Morrison, D. Delic, M.R. Yuce, J.-M. Redouté // IEEE Transaction on Very Large Scale Integration (VLSI) Systems. – 2019. – Vol 27,
№1. – P. 103–115.
[14] Kumar, S. Efficient Memory Built in Self-Test Address Generator Implementation / S. Kumar, M. Rajkumar //International Journal of Applied Engineering Research. –2015. – Vol 10, № 7. – P. 16797–16813.
[15] Saravanan, S. Design and Analysis of Low-Transition Address Generator / S. Saravanan, M. Hailu, G.M. Gouse, M. Lavanya, R. Vijaysai // Proc. of 6th EAI International Conference, ICAST, Bahir Dar, Ethiopia. – 2018. – P.
[16] Singh, B. Address Counter / Generators for Low Power Memory BIST / B. Singh, S. B. Narang, A. Khosla // IJCSI International Journal of Computer Science Issues. – 2011. – Vol. 8, Issue 4, № 1. – P. 561–567.
[17] Awad, A.N. Low Power Address Generator for Memory Built-In Self-Test / A.N. Awad, A.S. Abu-Issa //The Research Bulletin of Jordan ACM. – 2011. – Vol. II (III). –P. 52–56
[18] Boyd, S. Introduction to Applied Linear Algebra: Vectors, Matrices, and Least Squares / S. Boyd. – Cambridge, United Kingdom :University Printing House, 2018. – 463 p.
[19] Yarmolik, V.N. Generating Modified Sobol Sequences for Multiple Run March Memory Tests / V.N. Yarmolik, S.V. Yarmolik // Automatic Control and Computer Sciences. – 2013. –Vol. 47, № 5. – P. 242–247.
[20] Chen, T.Y. Quasi random testing / T.Y. Chen, R. Merkel // IEEE Trans. Reliability. – 2007. – Vol. 56, №3. – P. 562–568

Key Words:

MBIST, Built in memory self-test, pseudo-random numbers, pseudo-random sequences