SSRG - IJVSP - Volume 4 Issue 2 - May - August 2017

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S.No Title/Author Name Paper ID
1
High-Speed and Energy-Efficient Carry Skip Adder functioning under a extensive range of supply voltage Levels
- Amrutavarshini S H and Mr. S Pramod Kumar
IJVSP-V4I2P101
2
Fewer cost and superior functioning architecture of VSLI premeditated with Multiplication of Montgomery
- Meghana T.M and Pradeep Kumar S K
IJVSP-V4I2P102
3
Power Optimization Techniques for High Speed Processor Core in Sub 14nm Technology Node
- Kolusu Siva Mounica and Prashant K. Shah
IJVSP-V4I2P103
4
A 4-bit High Speed, Low Power Flash ADC by Employing Binary Search Algorithm
- Brahmaiah Throvagunta and Prashant K Shah
IJVSP-V4I2P104
5
Face Recognition for Access Control using PCA Algorithm
- Opeyemi Oyelesi and Akingbade Kayode Francis
IJVSP-V4I2P105
6
Noise optimization using FIR Filter
- Sandeep Kumar G and Nilam Chheda
IJVSP-V4I2P106
7
Semi-Custom design of functional unit block using data path methodology in data cache unit
- Aarti Patel and Prashant K.Shah
IJVSP-V4I2P107
8
Density Evolution of Low Density Parity Check codes over different channels
- P.Ravikiran and Mehul C. Patel
IJVSP-V4I2P108