SSRG - IJVSP - Volume 4 Issue 3 - September - December 2017

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S.No Title/Author Name Paper ID
1
Energy Consumption of Array-Based Logic Gates
- faraz Ahmed, Zaki Masood and Faiza Sabir
IJVSP-V4I3P101
2
Developed Cascaded Integrator for High Speed Wideband Frequency Variation
- D.Jesuva betisa and S.Chelsea mery
IJVSP-V4I3P102
3
Control Allowance of RISC manner Spending Clock Gating Method
- G.Jefryferrol and S.Maria Toshak
IJVSP-V4I3P103
4
D flip flops for Linear Response Shift Register in CMOS technology
- J.Hinay shelly and B.Craige Shreen
IJVSP-V4I3P104
5
Effectual Application of a digital apparatuses founded on embedded processor
- S.NelisaRejin and A.Sana Unita
IJVSP-V4I3P105
6
Advanced Signal Recognition Method for Path using FPGA
- R.Belly Ballot, T.Anisley and N.Addison
IJVSP-V4I3P106