SSRG - IJVSP - Volume 6 Issue 3 - September - December 2019

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S.No Title/Author Name Paper ID
1
Optimized Tsv Based 3d Integrated Circuit For Improve Power With Reduced Area Of Circuit
- Aditya Sharma, Mr. Dinesh Chand Gupta
IJVSP-V6I3P101
2
Modified radix 12 Multiplier for reducing area of designed circuit with reduce time delay
- Akshay Sharma, Mr. Dinesh Chand Gupta
IJVSP-V6I3P102
3
A Review on Low Power Memory Design Technique
- Bhumika Chaurasia, Nishi Pandey, Meha Shrivastava
IJVSP-V6I3P103
4
Comparison between the performance of the Simulated Annealing and Genetic Algorithms in Physical Conductor Orientation within FPGA
- Roba khega, Kamal Mahmoud Afisa, Mohammed Yassin Subaih
IJVSP-V6I3P104
5
Design of Programmable High Speed I/O S
- Aruna Rao B P, Shanthi Prasad M J
IJVSP-V6I3P105