Aninnovative Method in Designing Multiprocessor using Multi-Threading Techniques

International Journal of VLSI & Signal Processing

© 2016 by SSRG - IJVSP Journal

Volume 3 Issue 2

Year of Publication : 2016

Authors : Youmin Zhang and Joaquim Blesa

10.14445/23942584/IJVSP-V3I2P103

How to Cite?

Youmin Zhang and Joaquim Blesa, "Aninnovative Method in Designing Multiprocessor using Multi-Threading Techniques," SSRG International Journal of VLSI & Signal Processing, vol. 3,  no. 2, pp. 13-16, 2016. Crossref, https://doi.org/10.14445/23942584/IJVSP-V3I2P103

Abstract:

A quad-core processoris achip with four autonomouscomponents called cores whichdeliver and accomplish central processing unit. The quad processor core is an emerging trend used in many systematic and industrialclaims. In a distinct programmable device, FPGA with improving performance and gate capability can be implemented. The diplomatic issues in the embedded multiprocessor are thread safety. They have been occurred by the shared memory;while a thread safety is disrupted the processors could able to deliberate the equivalent value at the identical time. The two main impacts such as clock scaling procedures and micro architectural improvements are used to improve the processor performance. Consequentlyto rectify this problem, a new phenomenon called quad core architecture has been developed for system on a chip solicitation. Hence this system is designed by using VHDL and it accomplishesaninstantaneoususage of both parallel and distributed networks. The operations such as arithmetic, logical, shifting and bit manipulate are deliberated by using the full architecture of quad core processor. The projected quad processor core comprisesStandardized RISC processorsextracted with pipelined handlingcomponents, multi bus organization and I/O ports alongside with furtherefficientfeaturesnecessary to design embedded SoCresults. The implemented Quad core presentationdisputes such as speed, area, and power dissipation.

Keywords:

quad core processor, thread safety, parallel & distributed networks, RISC processors.

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