Fewer cost and superior functioning architecture of VSLI premeditated with Multiplication of Montgomery

International Journal of VLSI & Signal Processing
© 2017 by SSRG - IJVSP Journal
Volume 4 Issue 2
Year of Publication : 2017
Authors : Meghana T.M and Pradeep Kumar S K
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Meghana T.M and Pradeep Kumar S K, "Fewer cost and superior functioning architecture of VSLI premeditated with Multiplication of Montgomery," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 2, pp. 6-10, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I3P102

Abstract:

This paper is suggested forth with simple and efficacious Montgomery kind multiplication algorithm such that it is budgetary. Superior performance Montgomery modular multiplier can be enacted in congruence. The suggested multiplier acknowledges and turnouts of the data with the representations of binary utilized one level of Carry skip adder (CSA) to prohibit at the propagation at each summation type operation. This CSA can be premeditated to perform the respective operand at pre –guesstimation and the reformation of format basically from the format of carry save to the binary kind representation, which is following to a cost of low hardware and short cantankerous path lagging at extra clock cycles expense for making a culmination at one modular multiplication. To overcome this particularized weakness, configurable kind CSA could be one full adder or two of the serial half adders, which is suggested forth to lessen especially at the extra clock cycles for the pre-guesstimation operand and the format in reformation by a half. A mechanism is worked to investigate and consider skipping the unnecessary carry save addition operations in the one level CSA (CCSA) type architecture, while managing the short cantankerous path lagging, which has progressed.

Keywords:

 

Carry-save addition, Low-cost architecture, Montgomery modular multiplier, Publickey cryptosystem, Full carry save.

References:

[1] V. Bunimov, M. Schimmler, and B. Tolg, “A complexityeffective version of Montgomery’s algorithm,” in Proc. Workshop Complex. Effective Designs, May 2002.
[2] P. L. Montgomery, “Modular multiplication without trial division,” Math. Comput., vol. 44, no. 170, pp. 519–521, Apr. 1985.
[3] Y.-Y. Zhang, Z. Li, L. Yang, and S.-W. Zhang, “An efficacious CSA architecture for Montgomery modular multiplication,” Microprocessors Microsyst., vol. 31, no. 7, pp. 456–459, Nov. 2007.
[4] G. Perin, D. G. Mesquita, F. L. Herrmann, and J. B. Martins, “Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation,” in Proc. 6th Southern Program. Logic Conf., Mar. 2010, pp. 61– 66.
[5] J. Han, S. Wang, W. Huang, Z. Yu, and X. Zeng, “Parallelization of radix-2 Montgomery multiplication on multicore platform,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 12, pp. 2325–2330, Dec. 2013.