Noise optimization using FIR Filter

International Journal of VLSI & Signal Processing
© 2017 by SSRG - IJVSP Journal
Volume 4 Issue 2
Year of Publication : 2017
Authors : Sandeep Kumar G and Nilam Chheda
pdf
How to Cite?

Sandeep Kumar G and Nilam Chheda, "Noise optimization using FIR Filter," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 2, pp. 28-33, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I3P106

Abstract:

In procedure to make a more reasonable and precise pulse handling framework using ModelSim is created. Simple framework consumes wide room for pulse handling. In this design using ModelSim innovation has supplanted this impediment. It has turned into a to a great degree savvy methods for offstacking computationally escalated advanced signal preparing calculations to enhance general framework execution. The digital-filter execution in Verilog, using the committed equipment assets can viably accomplish application-particular coordinated circuit (ASIC)- like execution while lessening advancement time cost and dangers. A low-pass filter can be actualizing using Verilog HDL. MATLAB device with Verilog framework is most ideal approach to outline computerized framework. In plan of Finite Impulse Response (FIR) channel utilizing adder, coefficients and increase are utilized. Numerous Constant Multiplication (MCM) is the calculation which is utilized as a part of FIR planning to limit multifaceted nature of the circuit, expanded postponement and duplication utilizing huge range. These issues can be improved by utilizing new system known as digit-serial various steady augmentations. It decreases the manysided quality, postponement and area usage.

Keywords:

Ripple carry adder, Flip flop, ModelSim, Matlab.

References:

[1] Ray Goslin, Dr. San Jose, CA 95124 “A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific Digital Signal Processing Performance Gregory Digital Signal Processing” Program Manager Xilinx, Inc. 2100 Logic .
[2] WANG Jian-xing,YAO Qi-guo. Design of Chebyshev Low-pass Filter Based on MATLAB [J], Journal of Xinxiang University(Natural Science Edition),, 2012.2
[3] Chao Cheng and Keshab K Parhi. Low-Cost Parallel FIR Filter Structures With 2-Stage Parallelism [J].IEEE Transactions on Circuits and Systems I: Regular,2007,54(2):280~290.
[4] Hu Guang-shu. Digital signal processing-theory,algorithm and realizes[M]. 2nd ed.Beijing: Tsinghua University Press,2003:296~307.
[5] Chun Hok Ho,Chi Wai Yu and Leong P. Floating-Point FPGA: Architecture and Modeling IEEE Transactions on Very Large Scale Integration Systems, 2008,17(12): 1709~1718.
[6] D. E. Borth, I. A. Gerson, J. R. Haug, and C. D. Tho mpson “A flexible adaptive FIR filter VLSI IC”. IEEE Journ. Select. Areas Commun. SAC-6(3):494–503
[7] Lang, “ pole radius constraint,” IEEE Trans. Signal Processing, vol. 48,Nov. 2011.
[8] CHEN SH J, GUO J J. Design and implementation of raised cosine roll-off FIR filter based on FPGA[J].Telecom Power Technologies.2007, 24(2):19-21
[9] CHENG X P, QU B, LU G. An application of immune algorithm in FIR filter design[C].Nanjing: Proceedings of the 2003 International Conference on Neural Networks and Signal Processing,2003(1): 473-475.
[10] EVEN G, PAUL W J. On the design of IEEE compliant floating point units [J].IEEE Trans on Computers.2000,49(5):398-413.