Multiplier Design Incorporating Logarithmic Number System for Residue Number System in Binary Logic

International Journal of VLSI & Signal Processing
© 2018 by SSRG - IJVSP Journal
Volume 5 Issue 3
Year of Publication : 2018
Authors : Shalini R.V and Dr.P.Sampath
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How to Cite?

Shalini R.V and Dr.P.Sampath, "Multiplier Design Incorporating Logarithmic Number System for Residue Number System in Binary Logic," SSRG International Journal of VLSI & Signal Processing, vol. 5,  no. 3, pp. 11-22, 2018. Crossref, https://doi.org/10.14445/23942584/IJVSP-V5I3P102

Abstract:

Residue Number System (RNS) incorporates several significant features that are indispensible in Digital Signal Processing (DSP) applications. It includes higher operational speed, secured processing of data, carry free operations that reduces propagation of error among modules and so on. Multiplication process is the vital part of several DSP functions and hence design of such process using RNS system is gaining potential. For further improving the processing speed and security level of RNS, Multilevel-Residue Number System (MRNS) is introduced. This paper deals about the implementation of Logarithmic Number System (LNS) in RNS to propose the multiplication design based on Residue Logarithmic Number System (RLNS). Multilevel-Residue Number System (M-RNS) is incorporated in this research work introducing Multilevel-Residue Logarithmic Number System (M-RLNS) based multiplier design. Use of logarithmic numbers are restricted on accuracy constraints, hence improvement in accuracy is realized by employing error correction circuits. Area, Total Power Dissipation (TPD), delay and Power Delay Product (PDP) of the multiplication design proposed are tabulated for number of bits, N=8, 16 and 32 and the same is compared with the existing design.

Keywords:

 Residue Number System (RNS), Logarithmic Number System (LNS), Multilevel-Residue Number System (M-RNS), Multilevel-Residue Logarithmic Number System (M-RLNS), Error correction circuits.

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