SSRG - IJECE - Volume 4 Issue 12 - December 2017
| S.No | Title/Author Name | Paper ID |
|---|---|---|
| 1 |
Des IGN of Inexact Circuits using Gate-Level Pruning
|
IJECE-V4I12P101 |
| 2 |
Null Convention Logic (NCL) Design of Efficient Sorting Unit
|
IJECE-V4I12P102 |
| 3 |
Usage of Gain Cell Embedded Dram in Low Power Applications
|
IJECE-V4I12P103 |
| 4 |
Data Pattern Aware Error Prevention Technique: Survey
|
IJECE-V4I12P104 |