SSRG - IJVSP - Volume 2 Issue 1 - January - April 2015
| S.No | Title/Author Name | Paper ID |
|---|---|---|
| 1 |
Design a Low Power Double Tail Comparator using Gated Clock and Power Gating Techniques
|
IJVSP-V2I1P101 |
| 2 |
Architecture Design for an Adaptive Equalizer using LMS 2Tap filters
|
IJVSP-V2I1P102 |
| 3 |
High Performance and Low Power Asynchronous Data Sampling with Power Gated Double Edge Triggered Flip-Flop
|
IJVSP-V2I1P103 |
| 4 |
A Review on Area Efficient Parallel FIR Digital Filter Implementation
|
IJVSP-V2I1P104 |
| 5 |
Design and Simulation of 4*1 Mux Based on Low Power Design Techniques
|
IJVSP-V2I1P105 |