SSRG - IJVSP - Volume 4 Issue 3 - September - December 2017
| S.No | Title/Author Name | Paper ID |
|---|---|---|
| 1 |
Energy Consumption of Array-Based Logic Gates
|
IJVSP-V4I3P101 |
| 2 |
Developed Cascaded Integrator for High Speed Wideband Frequency Variation
|
IJVSP-V4I3P102 |
| 3 |
Control Allowance of RISC manner Spending Clock Gating Method
|
IJVSP-V4I3P103 |
| 4 |
D flip flops for Linear Response Shift Register in CMOS technology
|
IJVSP-V4I3P104 |
| 5 |
Effectual Application of a digital apparatuses founded on embedded processor
|
IJVSP-V4I3P105 |
| 6 |
Advanced Signal Recognition Method for Path using FPGA
|
IJVSP-V4I3P106 |