SSRG - IJVSP - Volume 6 Issue 3 - September - December 2019
| S.No | Title/Author Name | Paper ID |
|---|---|---|
| 1 |
Optimized Tsv Based 3d Integrated Circuit For Improve Power With Reduced Area Of Circuit
|
IJVSP-V6I3P101 |
| 2 |
Modified radix 12 Multiplier for reducing area of designed circuit with reduce time delay
|
IJVSP-V6I3P102 |
| 3 |
A Review on Low Power Memory Design Technique
|
IJVSP-V6I3P103 |
| 4 |
Comparison between the performance of the Simulated Annealing and Genetic Algorithms in Physical Conductor Orientation within FPGA
|
IJVSP-V6I3P104 |
| 5 |
Design of Programmable High Speed I/O S
|
IJVSP-V6I3P105 |