SSRG - IJVSP - Volume 2 Issue 1 - January - April 2015

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S.No Title/Author Name Paper ID
1
Design a Low Power Double Tail Comparator using Gated Clock and Power Gating Techniques
- T.Loganayaki and R.Ramya
IJVSP-V2I1P101
2
Architecture Design for an Adaptive Equalizer using LMS 2Tap filters
- P.S. Radhika and N.Porutchelvam
IJVSP-V2I1P102
3
High Performance and Low Power Asynchronous Data Sampling with Power Gated Double Edge Triggered Flip-Flop
- R. Aruna and S.Thenappan
IJVSP-V2I1P103
4
A Review on Area Efficient Parallel FIR Digital Filter Implementation
- Arunadevi A . ,Chitra K. , GunaNandhini S. , Raghupathi T. , and Rejusha M
IJVSP-V2I1P104
5
Design and Simulation of 4*1 Mux Based on Low Power Design Techniques
- Ira Parashar,Preeti Sikarwar, Rashmi Singh, Soumya Chauhan and Mrs. Shivani Saxena
IJVSP-V2I1P105