SSRG - IJVSP - Volume 3 Issue 3 - September - December 2016
| S.No | Title/Author Name | Paper ID | `
|---|---|---|
| 1 |
FPGA Implementation of BCG Signal Filtering Scheme by using Weight Update Process
|
IJVSP-V3I3P101 |
| 2 |
An enhanced fault tolerant system in the design of ALU using TMR technique
|
IJVSP-V3I3P102 |
| 3 |
An effective implementation of SOL’s technique for power and coding efficient VLSI architecture in DSRC applications
|
IJVSP-V3I3P103 |
| 4 |
Velocity regulator of AC motor with V/F controller
|
IJVSP-V3I3P104 |