Optimizing the Modified Booth Recoder for Fused Add-Multiply Operator
|International Journal of VLSI & Signal Processing|
|© 2015 by SSRG - IJVSP Journal|
|Volume 2 Issue 2|
|Year of Publication : 2015|
|Authors : Manju Mallayagari and G. Sahithi Reddy|
Manju Mallayagari and G. Sahithi Reddy, "Optimizing the Modified Booth Recoder for Fused Add-Multiply Operator" SSRG International Journal of VLSI & Signal Processing 2.2 (2015): 1-5.
Manju Mallayagari and G. Sahithi Reddy,(2015). Optimizing the Modified Booth Recoder for Fused Add-Multiply Operator. SSRG International Journal of VLSI & Signal Processing 2(2), 1-5.
This proposed method the design and simulation of Radix-8 Booth Encoding that can employ in DSP applications. As the Radix-8 Booth Encoder circuit produces n/3 the partial products in parallel manner. The proposed scheme effectively implements a newly recoding technique for modified booth recoding that ensures to implement the direct recoding of the multiplier in its Sum Modified Booth (SMB) form. Another vital advantage of S-MB algorithm that is well structured, simple and can be easily modified in order to apply either in signed or unsigned numbers, which consists of odd or even number of bits. Also Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Because of signed and unsigned multiplication operation is well performed by the same multiplier unit the required hardware and thus chip area reduces and this in turn reduces power dissipation and cost of a system. Finally Fused Add Multiply operator is optimized to increase the performance of complex arithmetic operation with three different recoding schemes S-MB1, S-MB2, S-MB3.The simulation is done through Verilog on xiling13.3 platform which provide accurate in calculating the various parameters.
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Array multiplier, Fused Add Multiply, Braun array multiplier, CLA, CSA, Radix-8 Booth Encoding multiplier, Signed-unsigned.