Analysis and Optimization of Power Consumption and Area of Domino Full Adder

International Journal of VLSI & Signal Processing
© 2015 by SSRG - IJVSP Journal
Volume 2 Issue 2
Year of Publication : 2015
Authors : B. Krishna Naga Deepthi and Dr.M.V.Subramanyam
: 10.14445/23942584/IJVSP-V2I2P104
MLA Style:

B. Krishna Naga Deepthi and Dr.M.V.Subramanyam, "Analysis and Optimization of Power Consumption and Area of Domino Full Adder" SSRG International Journal of VLSI & Signal Processing 2.2 (2015): 14-19.

APA Style:

B. Krishna Naga Deepthi and Dr.M.V.Subramanyam,(2015). Analysis and Optimization of Power Consumption and Area of Domino Full Adder. SSRG International Journal of VLSI & Signal Processing 2(2), 14-19.


In this paper we analyse different domino logic full adder circuits by considering area, power consumption and number of transistors as the three main parameters which plays an important role in digital design. We proposed a hybrid logic based domino full adder circuit which provides better performance in the above mentioned three parameters than the existing circuits. The two important applications of full adder 1-bit Alu and 2-bit Comparator of the proposed circuit is also presented. All the circuits are designed and simulated using DSCH and MICROWIND tool.


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Key Words:

Full adder, Domino logic, Area, power consumption, Alu, Comparator.