Light weight security coding using PRESENT algorithm for cryptography application

International Journal of VLSI & Signal Processing
© 2020 by SSRG - IJVSP Journal
Volume 7 Issue 2
Year of Publication : 2020
Authors : B. Akhil, Md Muzammil Shareef, B. Shalini,Dr.SK.Fairooz, Shaik Mohammed Rafi
: 10.14445/23942584/IJVSP-V7I2P101
pdf
Citation:
MLA Style:

B. Akhil, Md Muzammil Shareef, B. Shalini,Dr.SK.Fairooz, Shaik Mohammed Rafi, "Light weight security coding using PRESENT algorithm for cryptography application" SSRG International Journal of VLSI & Signal Processing 7.2 (2020): 1-5.

APA Style:

B. Akhil, Md Muzammil Shareef, B. Shalini,Dr.SK.Fairooz, Shaik Mohammed Rafi,(2020). Light weight security coding using PRESENT algorithm for cryptography application. SSRG International Journal of VLSI & Signal Processing 7(2), 1-5.

Abstract:

In this article, we are developing a security approach using a lightweight algorithm called "PRESNT". This security encryption is a round update process with 31 iterations and updates. Hardware requirements to develop multiple iterations of security are resource limiting, and PRESENT has a significant reduction in resource use. In this work, the focus is on implementing using Xilinx FPGA installation. It is proposed to implement the PRESENT algorithm using VHDL, timing process testing, coding verification and decoding.

References:

[1] J. Attridge, “An overview of hardware security modules”, SANS Institute, Info Sec Reading Room, 1 (2002), no. 1, 1-10.
[2] H. A. Alkhzaímí and M. M. Lauridsen, “Cryptanalysis of the Simon family of block ciphers”, Technical University of Denmark, Vol. 1, 2013, no. 1, 1-26.
[3] P. Valla and J. Kaps, “Lightweight cryptography for FPGAs”, Reconfigurable Computing and FPGAs, 2009. ReConFig ’09. International Conference on, 2009, 225- 230.
[4] A. Bogdanov, L. Knudsen, G. Leander, and C. Paarl, A. Poschmann, M. J. B. Robshaw, Y. Seurin, C. Vikkelsoe, “PRESENT: An Ultra-Lightweight Block Cipher, Chapter in Cryptographic Hardware and Embedded Systems - CHES 2007, Springer-Verlag Berlin Heidelberg, 2007, Ch. 5, 450-466.
[5] R. Azuero, E. Jacinto and J. Castano, “A low-memory implementation of 128 aes for 32 bits architectures”, in En Congreso Argentino de Sistemas Embebidos CASE 2012, 2012, 67-73.
[6] M. Kumar and A. Singhal, “Efficient implementation of advanced encryption standard (AES) for ARM based platforms”, 1st International Conference on Recent Advances in Information Technology (RAIT), 2012, 23-27.
[7] K. M. Abdellatif, R. Chotin-Avot and H. Mehrez, “Lightweight and compact solutions for secure reconfiguration of FPGAs”, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013, 1-4.
[8] J. Pospiil and M. Novotny, “Evaluating cryptanalytical strength of lightweight cipher PRESENT on reconfigurable hardware”, 15th Euromicro Conference on Digital System Design (DSD), 2012, 560-567.
[9] E. Kavun and T. Yalcin, “RAM-based ultra-lightweight FPGA implementation of PRESENT”, 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, 280-285.
[10] A. Aysu, E. Gulcan and P. Schaumont, “Simon says: Break area records of block ciphers on FPGAs," IEEE Embedded Systems Letters, 6 (2014), no. 2, 37-40.
[11] S. Feizi, A. Ahmadi and A. Nemati, “A hardware implementation of Simon cryptography algorithm”, 2014 4th International Conference on Computer and Knowledge Engineering (ICCKE), 2014, 245-250.
[12] Shuangqing Wei, J. Wang, R Yin, and J. Yuan, “Trade-off between security and performance in block ciphered systems with erroneous ciphertexts”, 8 (2013), no. 4, 636-645.
[13] C.-P. Fan and J.-K. Hwang, “Implementations of high throughput sequential and fully pipelined AES processors on FPGA”, International Symposium on Intelligent Signal Processing and Communication Systems, 2007. ISPACS 2007, 353-356.
[14] Chih-Peng Fan and Jun-Kui Hwang, “Implementations of high throughput sequential and fully pipelined AES processors on FPGA”, International Symposium on Intelligent Signal Processinq and Comunication Systems ISPACS 2007, 2007, 353-356.
[15] J. J. Tay, M. M. Wong and I. Hijazin, “Compact and low power AES block cipher using lightweight key expansion mechanism and optimal number of s- boxes”, 2014 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2014, 108-114.

Key Words:

Present, PFGA ,VHDL ,Cryptography ,Xilinx.