Design of A Low Power 16- Bit CSLA Using Binary To Excess-1 Converter
|International Journal of VLSI & Signal Processing|
|© 2020 by SSRG - IJVSP Journal|
|Volume 7 Issue 2|
|Year of Publication : 2020|
|Authors : Anjali Raman,Chirukoti Anusha,C.Sucharitha, Shaik Mohammed Rafi,Dr.SK.Fairooz|
Anjali Raman,Chirukoti Anusha,C.Sucharitha, Shaik Mohammed Rafi,Dr.SK.Fairooz, "Design of A Low Power 16- Bit CSLA Using Binary To Excess-1 Converter" SSRG International Journal of VLSI & Signal Processing 7.2 (2020): 11-13.
Anjali Raman,Chirukoti Anusha,C.Sucharitha, Shaik Mohammed Rafi,Dr.SK.Fairooz,(2020). Design of A Low Power 16- Bit CSLA Using Binary To Excess-1 Converter. SSRG International Journal of VLSI & Signal Processing 7(2), 11-13.
For math functions , the fastest adders used is Carry Select Adder ( CSLA) in many data processors. CSLA is an Application Specific Integrated Circuit (ASIC) developed by modifying the CSLA Regular Square Root Structure (SQRT). The main goal is a poster design that has less space and strength compared to the regular CSLA SQRT to assess the proposed design performance in terms of area and power with logical voltage and custom design. However, CSLA is not effective in the region because it uses multiple pairs of corrugation load additives (RCA) to generate a partial amount and a conversion taking into account the input entry then the final sum and the conversion specified by the multiplexers. The basic idea of this synthesis is to use BEC as an alternative of a RCA with a regular CSLA to achieve lower power and region consumption. Despite the delay, CSLA is more beneficial in that it requires low power and area consumption. The proposed design was developed using Verilog-HDL and compiled into XILINX ISE 14.7 Software Tool.
 B. Ramakumar, H.M.Kittur, and P.M.Kannan,"Low Power and Area Efficient Carry Select Adder", Verylarge scale integration Systems, IEEE Transaction on Volume :20,Issue:2,2012.
 Mr. VaibhavNerkar, Prof. SunitaParihar and Prof. Soni Chaturvedi, “Low power & Area efficient Carry Select Adder using CMOS Technology” , IRJET VOL 03, ISSUE 06, JUNE 2016
 Sohan Purohit and Martin Margala, ”Investigating The Impact Of Logic And Circuit Implementation On Full Adder Performance”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 7, July 2012 .
 Reena Rani, L.K. Singh, Neelam Sharma,” A Novel design of High Speed Adders Using Quaternary Signed Digit Number System”, International Journal of Computer and Network Security,Vol. 2, No. 9, September 2010.
 DeepaSinha, Tripti Sharma, k.G.Sharma, Prof.B.P.Singh, “Design and Analysis of low Power 1-bit Full Adder Cell”,IEEE, 2011.
 Padma Devi, Ashima Girdher and Balwinder Singh, “Improved Carry Select Adder with Reduced Area and Low Power Consumption”, International Journal of Computer Application, Vol 3.No.4, June 2010 .
 T. Y. Ceiang and M. J. Hsiao, ―Carry-select adder using single ripple carry adder,‖ Electron. Lett., vol. 34,
 O. J. Bedrij, “Carry-select adder,” IRE Trans. Electron. Comput., pp. 340–344, 62.
 J. M. Rabaey, M. Pedram, “Low Power Design Methodologies”, Kluwer Academic Publishers, 1996
 K. Roy and S. C. Prasad, “Low-Power CMOS VLSI Circuit Design”, John Wiley &Sons, 1999.
 S.Balaprasad, M.Jeyalakshmi, “Area Efficient Carry Select Adder with Low Power”, SSRG International Journal of Electrical and Electronics Engineering, vol 2, iss 2, 2015.
 Sohan Purohit and Martin Margala, ”Investigating The Impact Of Logic And Circuit Implementation On Full Adder Performance”, IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 20, no. 7, july 2012
 Santanu Maity, Bishnu Prasad De, Aditya Kr. Singh,” Design and Implementation of Low-Power High-Performance Carry Skip Adder”, International Journal of Engineering and Advanced Technology (IJEAT),ISSN: 2249 – 8958, Volume-1, Issue-4, April 2012.
Binary to Excess-1 Converters (BEC), Carry Select Adder (CSLA), squareroot (SQRT) CSLA architecture, Low power, Ripple Carry Adder(RCA).