Application of DFT on UART Implmenatation

International Journal of VLSI & Signal Processing
© 2020 by SSRG - IJVSP Journal
Volume 7 Issue 2
Year of Publication : 2020
Authors : Madhura R, Sharanbsav A, Vaibhav Krishnan, A.G Sai Tejas, Akshita Deep
: 10.14445/23942584/IJVSP-V7I2P104
MLA Style:

Madhura R, Sharanbsav A, Vaibhav Krishnan, A.G Sai Tejas, Akshita Deep, "Application of DFT on UART Implmenatation" SSRG International Journal of VLSI & Signal Processing 7.2 (2020): 14-28.

APA Style:

Madhura R, Sharanbsav A, Vaibhav Krishnan, A.G Sai Tejas, Akshita Deep,(2020). Application of DFT on UART Implmenatation. SSRG International Journal of VLSI & Signal Processing 7(2), 14-28.


Asynchronous serial communication is sometimes enforced by Universal Asynchronous Receiver Transmitter (UART), largely used for brief distance, low speed, low value information exchange between processor and peripherals. UART permits full duplex serial communication link, and is employed in electronic communication and system. there's a desire for realizing the UART perform a single chip. Further, style systems not full testability is hospitable the exaggerated chance of product failures and incomprehensible market opportunities. Also, there's a desire to confirm the info transfer is error proof. This targets the introduction of intrinsic self-take a look at (BIST) and standing register to UART, to beat the on top of 2 constraints of testability and information integrity. The 8-bit UART with standing register and BIST module is coded in Verilog HDL and synthesized and simulated using Vivado Hlx design edition and van be realized on FPGA if required. The results indicate that this model eliminates the requirement for higher finish, pricey testers and thereby it will scale back the event time and price. The expanding development of sub-micron innovation has brought about the trouble of testing. Design and test engineers must choose the option to acknowledge new obligations that had been performed by gatherings of experts in the earlier years. Design engineers who don't plan frameworks in light of full testability open themselves to the expanded chance of item disappointments and botched market chances. BIST is a plan strategy that permits a circuit to test itself. the test execution accomplished with the usage of BIST is demonstrated to be sufficient to balance the disincentive of the equipment overhead delivered by the extra BIST circuit. The procedure can give shorter test time contrasted with a remotely applied test and permits the utilization of minimal effort test gear during all phases of creation


[1] Liakot Ali, Roslina Sidek , Ishak Aris , Alauddin Mohd. Ali, Bambang Sunaryo Suparjo,” Design of a micro-UART for SoC application”, Science Direct, Computers and Electrical Engineering 30 (2004) 257–268, December 2004.
[2] T.D. Manoj Kumar Reddy, “Implementation and Customization of UART in Xilinx FPGA”. International Journal of Combined Research & Development (IJCRD), eISSN: 2321-225X; pISSN: 2321-2241 Volume: 2; Issue: 1; January – 2014.
[3] M.RAMAKRISHNA –Assistant Professor, Dept of ECE, SREE CHAITANYA INSTITUTE OF TECHNOLOGICAL SCIENCES.” NOVEL IMPLEMENTATION OF UART WITH BIST TECHNIQUE IN FPGA”, International Journal of Global Innovations -Vol.2, Issue. I, Paper Id: SP-V2-I1-005, ISSN Online: 2319-9245, May 2014.
[4] D.Monica satyavathi1, G.Anjaneyulu2 “ Implementation of BIST Technique in uart Serial communication”, Electronics and Communication Engineering Dept. M.V.G.R.College of Engineering Vizianagaram, India,” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 5, Ver. II (Sep-Oct. 2014), PP 21-29 e-ISSN: 2319 – 4200, Oct, 2014.
[5] AKSHATA SURENDRA SAVANT1, SANDRA BENJAMIN2 AND M Z KURIAN3 1M.Tech in VLSI and Embedded Systems, Department of ECE, SSIT, Tumakuru, Karnataka, India., “Design and Simulation of UART and Built-in-self-test Architecture in Verilog-HDL”, International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE) ISSN: 0976-1353 Volume 14 Issue 2 –APRIL 2015.
[6] M. Mamatha, Vijaykumar R. Urkude M. Tech in VLSI at Vignan Institute of Engineering and Technology IIAssociate Prof., Dept. of Electronics and Comm. Engg. in Vignan Institute of Engg. and Technology, “BIST Enabled UART for Real Time Interface Applications using FPGA” International Journal of Research in Electronics and Communication Technology (IJRECT 2015), IJRECT All Rights Reserved 10, ISSN: 2348 – 9065, ISSN: 2349 - 3143, Vol. 2, Issue 4 Oct. - Dec. 2015.
[7] Neeraj Pawar, “UART implementation with multiple input signature register for full fault coverage”, SCHOOL OF VLSI DESIGN AND EMBEDDED SYSTEMS NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA-136119, SESSION 2014-2016.
[8] V. Thirunavukkarasu, R.Saravanan and V.Saminadan” Performance of Low Power BISTArchitecture for UART” International Conference on Communication and Signal Processing, April 6-8, 2016, India.
[10] M.S.N. Shettennavar, Mr.B.N. Sachidanand, Mr.D.K.Gupta, Mr.V.M.Metigoudar Assistant Professor, Dept. of Electronics Engineering, DKTE’s Textile and Engineering Institute ,Ichalkaranji Maharashtra India.” Implementation of UART with BIST Technique “International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 03 Issue: 09, Sep-2016.
[11] E. Raghuveera1, K Hari Kishore2, Shaik Shoukat Vali3, and G. Siri Vennela Department of ECE, K L University, Vaddeswaram, Guntur, A.P, India, “VERILOG IMPLEMENTATION OF UART WITH BIST TECHNIQUE FOR TPG”, International Journal of Pure and Applied Mathematics, Volume 115 No. 7, 531-536 ,ISSN: 1311-8080 ,( ISSN: 1314-3395 url: , Special Issue, 2017
[12] P. Ramesh, Dr. D.N Rao, Dr. K. Srinivasa Rao, Assoc Professor, ECE Department Joginpally BR Egg College, ECE Department DRK Institute of science and “Power Reduction Testing Techniques of BIST, LFSR & ATPG for Low Power Circuits” International Journal of Engineering Research in Electronics and Communication Engineering (IJERECE) Vol 4, Issue 11, November 2017.
[13] Yogesh Kumar, Neeraj Pawar Assistant Professor, MITRC, Alwar, Rajasthan, India,” Implementation of built in self-test (BIST) enabled UART using FPGA for fault detection”. National Journal of Multidisciplinary Research and Development, ISSN: 2455-9040, Impact Factor: RJIF 5.22, Volume 3; Issue 1; January 2018
[14] S SANTHI PRIYA, G RAVIKISHORE Assistant Professor, Department of ECE, Vidya Jyothi Institute of Technology, Hyderabad, Telangana,” Design and analysis of UART based on BIST”, International Journal of Research, e-ISSN: 2348-6848, p-ISSN: 2348-795X, Volume 05 Issue 23, December 2018
[15] V K Ivanov, E V Nosov, “Serial communication protocol for FPGA-based systems”, International Youth Conference on Electronics, Telecommunications and Information Technologies 11–12 July 2019, Congress Centre of Peter the Great, St. Petersburg Polytechnic University, Russian Federation, Conf. Ser. 1326 012044, 1st Oct 2109.
[16] Biswajit Pandey, Abhishek Pandey, DM Akbar Hussain, “Low voltage Complementary Metal Oxide Semiconductor Energy efficient UART design on Spartan6 FPGA”, 11th International Conference on Computational Intelligence and Communication Networks, 2019.

[1] Tom Feist,” Vivado Design Suite” Xilinx, WP416 (v1.1) June 22, 2012.
[2] Vivado Design Suite User Guide “High-Level Synthesis”, Xilinx, UG902 (v2017.1) April 5, 2017

Key Words:

UART, BIST, Error check, Status register, LFSR