A VLSI IMPLEMENTATION OF HAMMING CODE ALGORITHM USING FPGA ARCHITECTURE

International Journal of VLSI & Signal Processing
© 2020 by SSRG - IJVSP Journal
Volume 7 Issue 2
Year of Publication : 2020
Authors : Vijayakumara Y M, Byregowda B K, Pradeep Kumar S, Raghav S, Nataraja M, Dr. S N Sheshappa
: 10.14445/23942584/IJVSP-V7I2P105
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Citation:
MLA Style:

Vijayakumara Y M, Byregowda B K, Pradeep Kumar S, Raghav S, Nataraja M, Dr. S N Sheshappa, "A VLSI IMPLEMENTATION OF HAMMING CODE ALGORITHM USING FPGA ARCHITECTURE" SSRG International Journal of VLSI & Signal Processing 7.2 (2020): 29-35.

APA Style:

Vijayakumara Y M, Byregowda B K, Pradeep Kumar S, Raghav S, Nataraja M, Dr. S N Sheshappa,(2020). A VLSI IMPLEMENTATION OF HAMMING CODE ALGORITHM USING FPGA ARCHITECTURE. SSRG International Journal of VLSI & Signal Processing 7(2), 29-35.

Abstract:

The communication theory has the issue of error correction, and detection has great practical importance. Error correction codes permit the detection and correction of errors that result from noise or other impairments during transmission from the transmitter to the receiver. Error correction schemes permit error localization and also give the possibility of correcting them. Error correction and detection schemes find use in implementations of reliable data transfer over noisy transmission links, data storage media (including dynamic RAM, compact discs), and other applications where data
integrity is important. Error correction avoids retransmission of the data, which can degrade system performance.
Hamming code is an error-correction code that can be used to detect single and double-bit errors and correct single-bit errors that can occur when
binary data is transmitted from one device into another. Hamming codes provide for FEC using a "block parity" mechanism that can be inexpensively
implemented. In general, their use allows the correction of single-bit errors and detection of two-bit errors per unit data, called a code word.

References:

[1] E. Khan , S. Lehmann ; H. Gunji , M. Ghanbari, “Iterative error detection and correction of coded video for wireless networks” IEEE Transactions on Circuits and Systems for Video Technology Year: 2004, Volume: 14, Issue: 12 .
[2] P. Perry ; Mingche Li ; Mao-Chao Lin ; Zhen Zhang, “Runlength limited codes for single error-detection and single error-correction with mixed type errors”, IEEE Transactions on Information Theory Year: 1998, Volume: 44, Issue: 4.
[3] Ashwini kumari P, , Byregowda B K, Vijayakumara Y M, Ravikumar H R , Dr S N Sheshappa, Pradeep kumar S"A Hardware Implementation Of Hazardous Gases Detection Using Robot" International Journal of Engineering Trends and Technology 67.7 (2019): 24-30.
[4] Liwen Liu, YiqiZhuang, LiZhang, HualianTang, SiwanDong, “Proactive correction coset decoding scheme based on SEC-DED code for multibit asymmetric errors in STT-MRAM”, Elsevier, Microelectronics Journal Volume 82, December 2018, Pages 92-100
[5] C. W. Slayman, "Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations," in IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 397-404, Sept. 2005, doi: 10.1109/TDMR.2005.856487.
[6] S. S. Sarnin, N. F. Nairn and W. N. S. W. Muhamad, "Performance evaluation of phase shift keying modulation technique using BCH code, Cyclic code and Hamming code through AWGN channel model in communication system," The 3rd International Conference on Information Sciences and Interaction Sciences, Chengdu, 2010, pp. 60- 65, doi: 10.1109/ICICIS.2010.5534715.
[7] J. Metzner, "Correction of Two (or Often More) Vector Symbol Errors With the Outer Structure of a Hamming Single Error Correcting Code," in IEEE Communications Letters, vol. 18, no. 12, pp. 2069-2072, Dec. 2014, doi: 10.1109/LCOMM.2014.2363665.
[8] S. G and R. N, "VLSI design of Parity check Code with Hamming Code for Error Detection and Correction," 2019 International Conference on Intelligent Computing and Control Systems (ICCS), Madurai, India, 2019, pp. 15-20, doi: 10.1109/ICCS45141.2019.9065790.
[9] Anlei Wang and N. Kaabouch, "FPGA based design of a novel enhanced error detection and correction technique," 2008 IEEE International Conference on Electro/Information Technology, Ames, IA, 2008, pp. 25-29, doi: 10.1109/EIT.2008.4554262.
[10] J. Singh and J. Singh, "A Comparative Study of Error Detection and Correction Coding Techniques," 2012 Second International Conference on Advanced Computing & Communication Technologies, Rohtak, Haryana, 2012, pp. 187-189, doi: 10.1109/ACCT.2012.2.
[11] T. Anwar, P. K. Lala and J. P. Parkerson, "A novel FPGA Architecture with Built-in Error Correction," 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007, Warsaw, 2007, pp. 1-4, doi: 10.1109/IMTC.2007.379193.
[12] S. Muppalla and K. R. Vaddempudi, "A novel VHDL implementation of UART with single error correction and double error detection capability," 2015 International Conference on Signal Processing and Communication Engineering Systems, Guntur, 2015, pp. 152-156, doi: 10.1109/SPACES.2015.7058236.
[13] R.Divyasharon and Dr.D.Sridharan, "Implementation of low power wireless sensor node with fault tolerance mechanism" SSRG International Journal of Electronics and Communication Engineering 3.4 (2016): 1-5.

Key Words:

communication, memory, code correction, Hamming code