FPGA Implementation of Optimized BIST Architecture for Testing of Logic Circuits

International Journal of VLSI & Signal Processing
© 2020 by SSRG - IJVSP Journal
Volume 7 Issue 2
Year of Publication : 2020
Authors : Ramya R, Madhura R
: 10.14445/23942584/IJVSP-V7I2P106
pdf
Citation:
MLA Style:

Ramya R, Madhura R, "FPGA Implementation of Optimized BIST Architecture for Testing of Logic Circuits" SSRG International Journal of VLSI & Signal Processing 7.2 (2020): 36-42.

APA Style:

Ramya R, Madhura R,(2020). FPGA Implementation of Optimized BIST Architecture for Testing of Logic Circuits. SSRG International Journal of VLSI & Signal Processing 7(2), 36-42.

Abstract:

Verification is used at each stage of VLSI design to ensure that the IC is working correctly, but most of the verification is done either at design time
or at the time of designing or fabricating the IC. Along with verification at the design level, it is necessary to verify the operation of the chip after
design and fabrication. Normally in such cases, it is done by placing it in the IC testing kit, which inserts all input combinations with comparing all output combinations to compare the correctness of the chip. But the cost of such kits is high and not easily available. As a result, it is essential to insert some extra logic inside the chip, which verifies the correctness of the chip. But it increases the area and power requirement of the chip. In this project, we have designed an efficient architecture of BIST to check the correctness of the design, which is simulated using the Xilinx ISE 14.5 design suite and VIVADO 2018.3 student version and is implemented on FPGA.

References:

[1] Preethy K John, Rony Antony P, “Optimized BIST Architecture for Memory Cores and Logic Circuits using CLFSR”, IEEE,2017
[2] Amit Kumar Panda, Praveena Rajput, Bhawna Shukla,” FPGA Implementation of 8,16,32 bit LFSR with Maximum Length Feedback Polynomial using VHDL”. 2012.
[3] P. Ramesh, Dr. D.N Rao, Dr. K. Srinivasa Rao, “Power Reduction Testing Techniques of BIST, LFSR & ATPG for Low Power Circuits”,2017.
[4] Pushpraj Singh Tanwar, Priyanka Srivatsava, “VHDL Implementation of Logic BIST Architecture for Multiplier Circuit for Test Coverage in VLSI Chips”, 2014.
[5] J. Praveen, M.N. Shanmukha Swamy, “BIST-Based Low Power Test Vector Generator and Minimising bulkiness of VLSI Architecture”, 2018.
[6] Ben John, Christy Mathew Philip, Agi Joseph, “Design and Implementation of (Built in Self Test) BIST for VLSI Circuits using Verilog”, 2015.
[7] L. Supriya, J. Lingaiah, G.Kalyan “FPGA Implementation of BIST (Built in Self Test) Enabled UART for Real Time Interface Applications”, 2015.
[8] Anju Rajput, “Designing of BIST Architecture of Generic Multipliers”, 2014.
[9] Shivshankar Mishra, Ram Racksha Tripathi, Devendra Kr. Tripathi,” Implementation of Configurable Linear Feedback Shift Register in VHDL”, 2016.
[10] Jamuna S, Dr. V K Agarwal, “Implementation of BIST Structure using VHDL for VLSI Circuits”, International Journal of Engineering and Technology, Issue no. 6, pp. 5041-5048, 2011.
[11] Mehboob Hasan Ahmed, Rutuja Jagtap, Roopal Pantode, and Prof. S. S. Phule, "An FPGA Chip Identification Generator using Configurable Ring Oscillator" SSRG International Journal of Electronics and Communication Engineering 3.4 (2016): 10-14.

Key Words:

Verification, VLSI design, IC testing kit, Efficient architecture, Xilinx FPGA