A Low Power Hybrid Bit-Adaptive Approximate Multiplier with LOD Guided Approximation and Fault Tolerant Adders for Image Processing Applications

International Journal of Electronics and Communication Engineering

© 2026 by SSRG - IJECE Journal

Volume 13 Issue 3

Year of Publication : 2026

Authors : Lokhanadam Vara Prasad, K. Venkata Ramanaiah

10.14445/23488549/IJECE-V13I3P107

How to Cite?

Lokhanadam Vara Prasad, K. Venkata Ramanaiah, "A Low Power Hybrid Bit-Adaptive Approximate Multiplier with LOD Guided Approximation and Fault Tolerant Adders for Image Processing Applications," SSRG International Journal of Electronics and Communication Engineering, vol. 13,  no. 3, pp. 84-98, 2026. Crossref, https://doi.org/10.14445/23488549/IJECE-V13I3P107

Abstract:

Energy-constrained digital signals, image-processing platforms, and machine-vision systems rely heavily on multipliers owing to their crucial role in managing power, area, and computation speed. Traditional high-precision multipliers suffer from heavy latency and power consumption caused by complex partial product generation and carry propagation paths, which are unsuitable for low-power real-time operation. To overcome these drawbacks, this paper proposes a Hybrid Bit Adaptive Approximate Multiplier (HBAM), which adaptively varies its computing precision according to the prominent value inside the inputs by adopting an effective Leading-One Detection (LOD) scheme, a fault-tolerant adaptive adder. The architecture minimizes unnecessary switching activity and redundant computation by bit-adaptive truncation involving partial protection of high-order bits, and selects a set of high-precision significant bits for accuracy. The implementation results demonstrate that the proposed HBAM achieves substantial improvements over state-of-the-art approximate multipliers. For 8 bit designs, HBAM achieved the lowest area (610 µm²), lowest power (0.59 mW), and fastest delay (0.91 ns). The 16-bit solution also reports about 2,080 um (2) area, 1.68 mW power, and 1.59 ns delay over competing structures such as TOSAM, PPC, AMA-x, and LOA by a factor of even orders of magnitude. Application-level evaluation on standard benchmark images also demonstrates that the proposed HBAM yields better smoothing and edge detection quality, with a PSNR up to 40.00 dB and SSIM of 0.995 for smoothing and a PSNR up to 33.50 dB/ SSIM of 0.940 for edge detection, respectively, all at low arithmetic error (MSE of down to 6.50). These results show that the proposed HBAM architecture provides an excellent tradeoff between low power consumption, high performance, and high image quality and is highly suited for next-generation low-power image processing and embedded vision systems.

Keywords:

Approximate Computing, Hybrid Bit-Adaptive Multiplier (HBAM) and Leading-One Detection (LOD), Image Processing, Edge Detection and Smoothing Filters; Energy-Efficient Multiplier Architecture.

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