Semi-Custom design of functional unit block using data path methodology in data cache unit

International Journal of VLSI & Signal Processing

© 2017 by SSRG - IJVSP Journal

Volume 4 Issue 2

Year of Publication : 2017

Authors : Aarti Patel and Prashant K.Shah

10.14445/23942584/IJVSP-V4I3P107

How to Cite?

Aarti Patel and Prashant K.Shah, "Semi-Custom design of functional unit block using data path methodology in data cache unit," SSRG International Journal of VLSI & Signal Processing, vol. 4,  no. 2, pp. 34-38, 2017. Crossref, https://doi.org/10.14445/23942584/IJVSP-V4I3P107

Abstract:

Chip design commences with the conception of an idea dictated by the market. These ideas are then translated into architectural and electrical specifications. The architectural specifications define the functionality and partitioning of the chip into several manageable blocks. A Functional Unit Block (FUB) is a small part of the micro-processor that is characterized by an RTL code. This project discusses the design of a structured data path functional unit block of a microprocessor. It explains the total flow of the back end design starting from implementing the schematic circuit from given RTL code using standard library cells to final layout. The design will be fulfilled by all the given constraints like operating frequency, timing violations, area, power, noise, reliability and circuit quality.

Keywords:

RTL , Functional Unit block , Formal Equivalence Verification.

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