FPGA Implementation of Optimized BIST Architecture for Testing of Logic Circuits

International Journal of VLSI & Signal Processing
© 2020 by SSRG - IJVSP Journal
Volume 7 Issue 2
Year of Publication : 2020
Authors : Ramya R, Madhura R
How to Cite?

Ramya R, Madhura R, "FPGA Implementation of Optimized BIST Architecture for Testing of Logic Circuits," SSRG International Journal of VLSI & Signal Processing, vol. 7,  no. 2, pp. 36-42, 2020. Crossref, https://doi.org/10.14445/23942584/IJVSP-V7I2P106


Verification is used at each stage of VLSI design to ensure that the IC is working correctly, but most of the verification is done either at design time
or at the time of designing or fabricating the IC. Along with verification at the design level, it is necessary to verify the operation of the chip after
design and fabrication. Normally in such cases, it is done by placing it in the IC testing kit, which inserts all input combinations with comparing all output combinations to compare the correctness of the chip. But the cost of such kits is high and not easily available. As a result, it is essential to insert some extra logic inside the chip, which verifies the correctness of the chip. But it increases the area and power requirement of the chip. In this project, we have designed an efficient architecture of BIST to check the correctness of the design, which is simulated using the Xilinx ISE 14.5 design suite and VIVADO 2018.3 student version and is implemented on FPGA.


Verification, VLSI design, IC testing kit, Efficient architecture, Xilinx FPGA


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