Asic Implementation of Energy Efficient Reduced Size Array Multiplier

International Journal of Electrical and Electronics Engineering
© 2018 by SSRG - IJEEE Journal
Volume 5 Issue 2
Year of Publication : 2018
Authors : K.Jayasurya, M.Sangeetha
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Citation:
MLA Style:

K.Jayasurya, M.Sangeetha, "Asic Implementation of Energy Efficient Reduced Size Array Multiplier" SSRG International Journal of Electrical and Electronics Engineering 5.2 (2018): 12-17.

APA Style:

K.Jayasurya, M.Sangeetha,(2018). Asic Implementation of Energy Efficient Reduced Size Array Multiplier. SSRG International Journal of Electrical and Electronics Engineering 5(2), 12-17.

Abstract:

A highly efficient carry free multiplication plays a vital role in arithmetic operations. A special addition mechanism employed in the proposed work processes the bits from higher order to lower order i.e. from most significant bit to least significant bit is used for improving the performance of the multiplier by reducing the critical path delay. This left to right mode operation results in the reduction of partial products. This is achieved by effectively using on-the fly conversion (OTFC) along with radix-4 full adders. It also results in discarding final addition in the most significant part during the ripple carry addition in the least significant part. This minimizes overall delay of the multiplier compared with the conventional partial product generation. The proposed LRRS (left-to-right reduced size) multiplier is implemented with optimized on-the fly conversion circuit to reduce the multiplier complexity. Compared with conventional left-to-right multipliers the proposed full length multiplier and its truncated version results in reduction of area, power and delay. Finite Impulse Response filter involves multiplications, additions and shifting operations. As the multiplier is the slowest element in the system, it will affect the performance of the FIR filter. In this case, the reduced size, energy-efficient left-to-right array multiplier is designed which reduces the area, power and delay of the multiplier unit. Therefore the area is reduced with the increase in speed of operation and low power consumption in the multiplier unit of FIR filter which serves as the Application Specific IC.

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Key Words:

Left-to-right reduced size, on-the fly conversion, array reduction, truncated multiplier, FIR Filter.