Area Efficient Carry Select Adder with Low Power

International Journal of Electrical and Electronics Engineering
© 2015 by SSRG - IJEEE Journal
Volume 2 Issue 2
Year of Publication : 2015
Authors : S.Balaprasad, M.Jeyalakshmi
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Citation:
MLA Style:

S.Balaprasad, M.Jeyalakshmi, "Area Efficient Carry Select Adder with Low Power" SSRG International Journal of Electrical and Electronics Engineering 2.2 (2015): 1-5.

APA Style:

S.Balaprasad, M.Jeyalakshmi,(2015). Area Efficient Carry Select Adder with Low Power. SSRG International Journal of Electrical and Electronics Engineering 2(2), 1-5.

Abstract:

Carry SeLect Adder (CSLA) is known to be the fastest adder among the Conventional adder structures. Carry select adders provides a good compromise between cost, area and performance among carry propagation adders. Due to its less complex structure, there is still scope for obtaining better design Carry SeLect Adder (CSLA) architecture designs for power optimization combined with better performance. The conventional CSLA architecture uses dual RCAs which has large area consuming.Proposed technique eliminates all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the Carry Select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. Due to its small carry-output delay,the proposed CSLA design is a good candidate for SQuare-RooT (SQRT) CSLA.

References:

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Key Words:

 Adder, Area efficient, Boolean logic.