Area Efficient Carry Select Adder with Low Power
|International Journal of Electrical and Electronics Engineering|
|© 2015 by SSRG - IJEEE Journal|
|Volume 2 Issue 2|
|Year of Publication : 2015|
|Authors : S.Balaprasad, M.Jeyalakshmi|
S.Balaprasad, M.Jeyalakshmi, "Area Efficient Carry Select Adder with Low Power" SSRG International Journal of Electrical and Electronics Engineering 2.2 (2015): 1-5.
S.Balaprasad, M.Jeyalakshmi,(2015). Area Efficient Carry Select Adder with Low Power. SSRG International Journal of Electrical and Electronics Engineering 2(2), 1-5.
Carry SeLect Adder (CSLA) is known to be the fastest adder among the Conventional adder structures. Carry select adders provides a good compromise between cost, area and performance among carry propagation adders. Due to its less complex structure, there is still scope for obtaining better design Carry SeLect Adder (CSLA) architecture designs for power optimization combined with better performance. The conventional CSLA architecture uses dual RCAs which has large area consuming.Proposed technique eliminates all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the Carry Select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. Due to its small carry-output delay,the proposed CSLA design is a good candidate for SQuare-RooT (SQRT) CSLA.
 Basant Kumar Mohanty, ―Area-Delay Power Efficient Carry Select Adder,IEEE Transactions On Circuits And Systems—Ii: Express Briefs, Vol. 61, No. 6, June 2014.
 He, Y. Chang, C. H. and Gu, J. ―An Area Efficient 64- Bit Square Root Carry-Select Adder for Low Power Applications, in Proc. IEEE Int. Symp. Circuits Syst., vol.4, pp. 4082–4085, 2005.
 J. M. Rabaey, Digital Integrated Circuits, IEEE Trans. on VLSI Systems, 2003.
 Ramkumar, B. and Harish M Kittur, (2011) ‗Low Power and Area Efficient Carry Select Adder‘, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1-5.
 B. Ramkumar and Harish M. Kittur ―Low-Power and Area-Efficient Carry Select Adder, IEEE transactions on very large Scale integration (VLSI) systems, vol. 20, pp.371-375, February 2012.
 Sara deep Singh and Dilip Kumar ―Design of Area and Power Efficient Modified Carry Select Adder, International Journal of Computer Applications, vol.33, pp. 14-18, November 2011.
 O. Bedrij, ―Carry Select Adder, IRE Trans. on Electronic Computers, vol. EC-11, pp. 340- 346, 1962.
 Mr. C. S. Manikandababu ― An Efficient Carry Select Adder architecture for VLSI hardware implementation, IJMIE, vol.2, pp.610-622, May 2012.
 T. Y. Ceiang and M. J. Hsiao, ―Carry-select adder using single ripple carry adder, vol. 34, No. 22, pp. 2101–2103, Oct. 1998.
 O. Bedrij, ―Carry Select Adder, IRE Trans. on Electronic Computers,Vol. EC-11, pp. 340-346, 1962.
 Ramkumar, B. Kittur, H.M. and Kannan, P (2010) ‗ASIC Implementation of Modified Faster Carry Save Adder‘, Eur. J. Sci. Res., Vol.42, No.1, pp.53–58.
Adder, Area efficient, Boolean logic.