SSRG - IJVSP - Volume 5 Issue 3 - September - December 2018
| S.No | Title/Author Name | Paper ID |
|---|---|---|
| 1 |
Increasing Fault Coverage in Benchmark Circuit using Design for Testability and Test Pattern Generation using 6NCA
|
IJVSP-V5I3P101 |
| 2 |
Multiplier Design Incorporating Logarithmic Number System for Residue Number System in Binary Logic
|
IJVSP-V5I3P102 |
| 3 |
Parametric Variations of Transistor Doping Profiles for Ultra Low Power Applications
|
IJVSP-V5I3P103 |