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An Efficient Implementation of Multipliers for ASIC Implementations

International Journal of VLSI & Signal Processing
© 2016 by SSRG - IJVSP Journal
Volume 3 Issue 1
Year of Publication : 2016
Authors : K.Sucharitha and P. Rahul Reddy
10.14445/23942584/IJVSP-V3I1P101
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How to Cite?

K.Sucharitha and P. Rahul Reddy, "An Efficient Implementation of Multipliers for ASIC Implementations," SSRG International Journal of VLSI & Signal Processing, vol. 3,  no. 1, pp. 1-4, 2016. Crossref, https://doi.org/10.14445/23942584/IJVSP-V3I1P101

Abstract:

Nowadays modular multiplication of long integers is a significant building block for cryptographic algorithms. Even thoughnumerous FPGA accelerators have been proposed for large modular multiplication, earlier systems have been based on basically on O (N2) algorithms. In this paper, we present a Montgomery multiplier that includes the more effective Karatsuba algorithm which is O (N (log 3/ log 2)). This system is parameterizable to different bitwidths and makes exceptional use of both embedded multipliers and finegrained logic. The design has expressively lower LUTdelay productand multiplier-delay product related with former designs.

Keywords:

 Cryptograph, FPGA, Galois field, Karatsuba Multiplier.

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