Architecture for Matching of Data Encoded with Hard Systematic Error Correcting Codes using Verilog HDL

International Journal of Communication and Media Science

© 2014 by SSRG - IJCMS Journal

Volume 1 Issue 2

Year of Publication : 2014

Authors : G.Gopperum devi

10.14445/2349641X/IJCMS-V1I3P101

How to Cite?

G.Gopperum devi, "Architecture for Matching of Data Encoded with Hard Systematic Error Correcting Codes using Verilog HDL," SSRG International Journal of Communication and Media Science, vol. 1,  no. 2, pp. 16-10, 2014. Crossref, https://doi.org/10.14445/2349641X/IJCMS-V1I3P101

Abstract:

Data comparison is widely used in computing system to perform many operation. Where incoming information is needs to be compared with a piece of stored data to locate the matching entry. If both incoming bits and stored bits are matching means there is no error if mismatched means some type of error will occurred like random error or burst error. To detect and correct the error here error correcting codes are used. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance. The proposed architecture examines whether the incoming data matches the stored data if a certain number of burst errors are corrected. The basic function of the BWA is to count the number of 1’s among its input bits. It consists of multiple stages of HAs where each output bit of a HA is associated with a weight. The HAs in a stage are connected in a butterfly form so as to accumulate the carry bits and the sum bits of the upper stage separately.

Keywords:

-error correcting codes, hamming distance, data comparison, parity matrix.

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