Machine Learning-Aided Test Pattern Generation for VLSI Circuits: A Decision Tree Regressor Approach

International Journal of Electronics and Communication Engineering
© 2025 by SSRG - IJECE Journal
Volume 12 Issue 11
Year of Publication : 2025
Authors : Sima K Gonsai, Usha Mehta
pdf
How to Cite?

Sima K Gonsai, Usha Mehta, "Machine Learning-Aided Test Pattern Generation for VLSI Circuits: A Decision Tree Regressor Approach," SSRG International Journal of Electronics and Communication Engineering, vol. 12,  no. 11, pp. 228-239, 2025. Crossref, https://doi.org/10.14445/23488549/IJECE-V12I11P119

Abstract:

As the demand for complex IC, high-performance computing increases, IC technology needs to evolve quickly. It relies on the technology node shrinking. Due to the highly complex nature of the chips, designing and testing circuits becomes an extremely challenging and crucial task. To ensure chip reliability, IC testing is performed. It is one of the most important, complex, time-consuming, and necessary tasks. To validate the chip, Testing ensures the integrity of the chip by verifying the functionality, timing, and interconnections. Machine learning empowers the world by enhancing automation, data-driven decision-making, and optimization across all domains, including healthcare, finance, security, chip design, and manufacturing. This work demonstrates the role of Machine Learning (ML) in Automatic Test Pattern Generation (ATPG) for digital VLSI circuits and contributes to an alternative approach for test data generation. Compared to the ATALANTA tool, the Decision Tree Regressor(DTR) model achieved the best score, with an 18.1% reduction in test pattern count while maintaining the same fault coverage. For almost all benchmark circuits, the DTR model provides either superior fault coverage compared to the ATALANTA tool or a reduced test pattern count at equivalent fault coverage.

Keywords:

Automatic Test Pattern Generation, Decision Tree Regression, Fault Coverage, IC Testing, Machine Learning.

References:

[1] Wenxing Li et al., “SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning,” Proceedings of the 61st ACM/IEEE Design Automation Conference, pp. 1-6, 2024.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Yassine Attaoui et al., “Machine Learning in VLSI Design: A Comprehensive Review,” Journal of Integrated Circuits and Systems, vol. 19, no. 2, pp. 1-14, 2024.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Wenji Fang et al., “A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA,” arXiv Preprint, pp. 1-62, 2025.
[CrossRef] [Google Scholar] [Publisher Link]
[4] User's Guide for ATALANTA. Virginia Polytechnic & State University, The GitHub Website, 2025. [Online]. Available: https://github.com/hsluoyz/Atalanta
[5] Renjian Pan et al., “Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network Model,” 2019 IEEE 37th VLSI Test Symposium (VTS), Monterey, CA, USA, pp. 1-6, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[6] Harshad Dhotre et al., “Machine Learning-based Prediction of Test Power,” 2019 IEEE European Test Symposium (ETS), Baden, Germany, pp. 1-6, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Kai-Chieh Yang et al., “ATPG and Test Compression for Probabilistic Circuits,” 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, pp. 1-4, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Spencer Millican et al., “Applying Neural Networks to Delay Fault Testing : Test Point Insertion and Random Circuit Training,” 2019 IEEE 28th Asian Test Symposium (ATS), Kolkata, India, pp. 13-135, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Hauyu Yang et al., “Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning,” Proceedings of the 54th Annual Design Automation Conference 2017, Austin TX, USA, pp. 1-6, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Aysa Fakheri Tabrizi et al., “Eh ? Predictor : A Deep Learning Framework to Identify Detailed Routing Short Violations from a Placed Netlist,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 6, pp. 1177-1190, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[11] Kurt Hornik, Maxwell Stinchcombe, and Halbert White, “Multilayer Feedforward Networks are Universal Approximators,” Neural Networks, vol. 2, no. 5, pp. 359-366, 1989.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Maithra Raghu et al., “On the Expressive Power of Deep Neural Networks,” 34th International Conference on Machine Learning, vol. 70, pp. 2847-2854, 2017.
[Google Scholar] [Publisher Link]
[13] Yuzhe Ma et al., “High Performance Graph Convolutional Networks with Applications in Testability Analysis,” Proceedings of the 56th Annual Design Automation Conference 2019, Las Vegas NV, USA, pp. 1-6, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Kevin Eykholt et al., “Robust Physical-World Attacks on Deep Learning Visual Classification,” 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition, Salt Lake City, UT, USA, pp. 1625-1634, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[15] R. Selvarasan, and G. Sudhagar, “An Overview on Strategies to Perform VLSI Testing Productively Utilizing BIST,” International Journal of Advanced Networking and Applications, vol. 16, no. 2, pp. 6342-6348, 2024.
[Google Scholar] [Publisher Link]
[16] Jeffrey E. Nelson, Wing Chiu Tam, and R. D. Blanton, “Automatic Classification of Bridge Defects,” 2010 IEEE International Test Conference, Austin, TX, USA, pp. 1-10, 2010.
[CrossRef] [Google Scholar] [Publisher Link]
[17] Zipeng Li et al., “Test-Cost Optimization in a Scan-Compression Architecture Using Support-Vector Regression,” 2017 IEEE 35th VLSI Test Symposium (VTS), Las Vegas, NV, USA, pp. 1-6, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Kaiming Fu, Yulu Jin, and Zhousheng Chen, “Test Set Optimization by Machine Learning Algorithms,” 2020 IEEE International Conference on Big Data (Big Data), Atlanta, GA, USA, pp. 5673-5675, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[19] A. Karthikeyan, and N. Rajeswaran, “Design and Implementation of Multiple Fault Diagnosis on VLSI Circuits using Artificial Neural Networks,” International Journal of Advances in Engineering & Technology, vol. 3, no. 2, pp. 685-695, 2012. [Google Scholar] [Publisher Link]
[20] Animesh Basak Chowdhury et al., “Robust Deep Learning for IC Test Problems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 1, pp. 183-195, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[21] Hideo Fujiwara, “ISCAS ’ 85 Benchmarks : Special Session on ATPG and Fault Simulation,” 1985 IEEE International Symposium on Circuits and Systems, Kyoto Hotel, Kyoto, Japan, pp. 1-7, 1985.
[Google Scholar]
[22] M. Lipovský et al., “A New User-Friendly ATPG Platform for Digital Circuits,” 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Kosice, Slovakia, pp. 1-4, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[23] Fangming Ye et al., “Board-Level Functional Fault Diagnosis using Multikernel Support Vector Machines and Incremental Learning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 2, pp. 279-290, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[24] Manjari Pradhan et al., “Predicting X -Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 12, pp. 2343-2356, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[25] Shi Jin et al., “Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 6, pp. 985-998, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[26] Soumya Mittal, and R.D. Blanton, “LearnX : A Hybrid Deterministic-Statistical Defect Diagnosis Methodology,” 2019 IEEE European Test Symposium (ETS), Baden-Baden, Germany, pp. 1-6, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[27] Yu Huang et al., “Scan Chain Diagnosis based on Unsupervised Machine Learning,” 2017 IEEE 26th Asian Test Symposium (ATS), Taipei, Taiwan, pp. 225-203, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[28] Manjari Pradhan, and Bhargab B. Bhattacharya, “A Survey of Digital Circuit Testing in the Light of Machine Learning,” Wiley Interdisciplinary Reviews: Data Mining and Knowledge Discovery, vol. 11, no. 1, pp. 1-18, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[29] Garima Thakur, Shruti Jain, and Harsh Sohal, “Measurement : Sensors “Current Issues and Emerging Techniques for VLSI Testing - A Review,” Measurement: Sensors, vol. 24, pp. 1-9, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[30] Stephan Eggersglüß et al., “On Optimization-based ATPG and its Application for Highly Compacted Test Sets,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 12, pp. 2104-2117, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[31] S. Biswas et al., Automatic Test System for Testing VLSI Circuits, 2017.
[Google Scholar]
[32] H.K. Lee, and D.S. Ha, “Atalanta: An Efficient ATPG for Combinational Circuits,” Technical Report, Department of Electrical Engineering, Virginia Polytechnic Institute and State University, 1993.
[Google Scholar]