A Novel FPGA Design with Hybrid LUT / MUX Architecture
|International Journal of Electronics and Communication Engineering|
|© 2016 by SSRG - IJECE Journal|
|Volume 3 Issue 11|
|Year of Publication : 2016|
|Authors : E.Ganesan and V.Sakthivel|
How to Cite?
E.Ganesan and V.Sakthivel, "A Novel FPGA Design with Hybrid LUT / MUX Architecture," SSRG International Journal of Electronics and Communication Engineering, vol. 3, no. 11, pp. 6-8, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I11P112
Field programmable gate arrays (FPGAs) are increasingly used as the computing platform for fast and energy efficient execution of recognition, mining, and search applications. Approximate computing is one promising method for achieving energy efficiency. Compared with most prior works on approximate computing, which target approximate processors and arithmetic blocks. Hybrid configurable logic block architectures for field programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction.
hardened multiplexers are evaluated toward the goal of higher logic density and area reduction.
 I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” in Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays. ACM New York, NY, USA, 2006, pp. 21–30.
 K. Wu and Y. Tsai, “Structured ASIC, Evolution or Revolution,” April 2004, pp. 103–106.
 T. Okamoto, T. Kimoto, and N. Maeda, “Design Methodology and Tools for NEC Electronics Structured ASIC,” April 2004, pp. 90–96.
 J. Pistorius, M. Hutton, J. Schleicher, M. Iotov, E. Julias, and K. Tharmalignam, “Equivalence Verification of FPGA and Structured ASIC Implementations,” August 2007, pp. 423–428.
 H. Parvez, Z. Marrakchi, and H. Mehrez, “ASIF: Application Specific Inflexible FPGA,” in International Conference on Field- Programmable Technology, 2009. FPT 2009, 2009, pp. 112–119.
 V. Betz and J. Rose, “VPR: A New Packing Placement and Routing Tool for FPGA research,” International Workshop on FPGA, pp. 213– 22, 1997.
 G. Lemieux, E. Lee, M. Tom, , and A. Yu, “Directional and singledriver wires in fpga interconnect,” in IEEE Conference on FPT, 2004,pp. 41–48.
 Z. Marrakchi, H. Mrabet, E. Amouri, and H. Mehrez, “Efficient tree topology for fpga interconnect network,” in ACM Great Lakes Symposium on VLSI, 2008, pp. 321–326.
 L. Sterling and E. Shapiro, The Art of Prolog, 2nd ed. Cambridge, MA, USA: MIT Press, Mar. 1994.
 A. K. Mishra, R. Barik, and S. Paul, “iACT: A softwarehardware framework for understanding the scope of approximate computing,” in Proc. Workshop Approx. Comput. Across Syst. Stack (WACAS), Salt Lake City, UT, USA, 2014.
 C. Alvarez, J. Corbal, and M. Valero, “Fuzzy memoization for floatingpoint multimedia applications,” IEEE Trans. Comput., vol. 54, no. 7, pp. 922–927, Jul. 2005.
 C. Á. Martínez, J. C. S. Adrián, and M. V. Cortés, “Dynamic tolerance region computing for multimedia,” IEEE Trans. Comput., vol. 61, no. 5, pp. 650–665, May2012.