A Novel FPGA Design with Hybrid LUT / MUX Architecture

International Journal of Electronics and Communication Engineering

© 2016 by SSRG - IJECE Journal

Volume 3 Issue 11

Year of Publication : 2016

Authors : E.Ganesan and V.Sakthivel

10.14445/23488549/IJECE-V3I11P112

How to Cite?

E.Ganesan and V.Sakthivel, "A Novel FPGA Design with Hybrid LUT / MUX Architecture," SSRG International Journal of Electronics and Communication Engineering, vol. 3,  no. 11, pp. 6-8, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I11P112

Abstract:

Field programmable gate arrays (FPGAs) are increasingly used as the computing platform for fast and energy efficient execution of recognition, mining, and search applications. Approximate computing is one promising method for achieving energy efficiency. Compared with most prior works on approximate computing, which target approximate processors and arithmetic blocks. Hybrid configurable logic block architectures for field programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction.

Keywords:

 hardened multiplexers are evaluated toward the goal of higher logic density and area reduction.

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