QCA Design of Encoder for Low Power Memory Applications
|International Journal of Electronics and Communication Engineering|
|© 2016 by SSRG - IJECE Journal|
|Volume 3 Issue 11|
|Year of Publication : 2016|
|Authors : K.Bharathi and S.Vijayakumar|
How to Cite?
K.Bharathi and S.Vijayakumar, "QCA Design of Encoder for Low Power Memory Applications," SSRG International Journal of Electronics and Communication Engineering, vol. 3, no. 11, pp. 13-15, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I11P114
A decoder is important component of memory, for address decoding and encoding. The size of Complementary Metal Oxide Semiconductor (CMOS) transistor keeps shrinking to increase the density on chip in accordance with Moore’s Law. The scaling affects the device performance due to constraints like heat dissipation and power consumption. A Quantum dot Cellular Automata (QCA) is an alternative to CMOS.QCA offers higher speed, lower power consumption and higher density. In non reversible gates some amount of power loss is involved. Interest in reversible logic offers reduced heat dissipation and increases the speed. It is a new transistor-less computation in nanotechnology. In this project propose a reversible gate based decoder architecture. It provides reversibility and area minimization. QCA designer tool has been used to validate the performance of reversible decoders
QCA designer tool has been used to validate the performance of reversible decoders.
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