Design of Low Power Sense Amplifier Flip Flop using GDI and FinFET Techniques

International Journal of Electronics and Communication Engineering
© 2018 by SSRG - IJECE Journal
Volume 5 Issue 5
Year of Publication : 2018
Authors : M.Aruna devi and A.Jagadeeswaran
How to Cite?

M.Aruna devi and A.Jagadeeswaran, "Design of Low Power Sense Amplifier Flip Flop using GDI and FinFET Techniques," SSRG International Journal of Electronics and Communication Engineering, vol. 5,  no. 5, pp. 4-10, 2018. Crossref,


This proposal is based on the analysis of basic memory elements called flip-flops. In order to achieve a design that is both highly efficient and high performance, it is necessary to take care while designing these memory elements i.e. flip-flops and latches. The proposed technique enhanced with new SAFF using GDI technique in which GDI latch has been used. The proposed method is designed with dual gate FinFET device to improve performance of this device which is most frequency used in memory devices. FinFET is a promising alternative to conventional MOSFET - which has reached its limits and has too much leakage for too little performance gain. FinFET is being recommended as the basis for future IC processes because of its power/performance benefits, scalability, superior controls over short channel effects etc.The FinFET based circuits provides better results in switching activity when compare with conventional CMOS technology. It results power efficient circuits. The new flip-flop uses a new output stage latch topology using GDI technique that significantly reduces power consumption and has improved power-delay product (PDP). In circuit implementation, transistor sizes are optimized with respect to the power delay product (PDP). The simulation results shows that the proposed method is more efficient than the conventional circuits, while considering the parameters like PDP, average power consumption, and leakage power consumption. Simulations are carried out by TANNER EDA(T-SPICE)<-SPICE and finally the power comparison is done with various flip flops.


Flip-flop, GDI, FinFET, Low Power.


[1] Adarsh Kumar Agrawal , Shivshankar Mishra, and Nagaria, "Proposing a Novel Low-Power High-Speed Mixed GDI Full Adder Topology", accepted in Proceeding of IEEE International Conference on Power, Control and Embedded System (ICPCES),2010. 
[2] Ritesh Kumar Yadav, Rajesh Mehra,"Design and Implementation of T-Flip Flop using GDI Techniques",International Journal of Engineering Trends and Technology (IJETT),Volume-36 Number-2 2016. 
[3] Aniruddha Ghosal and Biswarup Mukherjee, “Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer,” IEEE 2nd Intl. Conf. on Recent Trends in Information Systems,2015. 
[4] Behjat Forouzandeh, Soolmaz Abbasalizadeh” Full-Adder Design with GDI Cell and Independent Double Gate Transistor”, 20th Iranian Conf. on Electrical Engineering,2012 
[5] A. Islam,A, Mohd.Hasan,“Variability Analysis and FinFET-based Design of XOR and XNOR Circuit,” International Conference on Computer & Communication Technology (ICCCT), pp. 239-245,2011. 
[6] T.Loganayaki, R.Ramya,"Design a Low Power Double Tail Comparator using Gated Clock and Power Gating Techniques",International Journal of VLSI & Signal Processing (SSRG-IJVSP),Volume2 Issue1 2015. 
[7] H. Kawaguchi. and T. Sakurai,“A reduced clock-swing flip-flop (RCSFF) for 63% power reduction,” IEEE J. Solid-State Circuits, vol. 33, no. 5,pp. 807–811,1998. 
[8] N. Kawai,“A fully static topologically-compressed 21-transistor flip-flop with 75% power saving,” IEEE J. Solid-State Circuits, vol. 49, no. 11,pp. 2526–2533,2014. 
[9] Kahkashan Ali, Tarana Afrin Chandel,"Minimization of Power for the Design of an Optimal Flip Flop",International Journal of Electronics and Communication Engineering (SSRG - IJECE),Volume 4 Issue 7 2017. 
[10] T.J King,“FinFETs for nanoscale CMOS digital integrated circuits,” in Proc. Int. Conf.Computer-Aided Design, Nov. 2005, pp. 207–210. 
[11] B.S Kong, S.S Kim, and Y.H Jun,“Conditional- capture flip-flop for Statistical power reduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8,pp. 1263–1271,2011. 
[12] Sana Ur Rahman, Tarana Afrin Chandel,"Schematic Design and Layout of Flipflop using CMOS Technology"International Journal of Electronics and Communication Engineering (SSRG-IJECE),Volume-4 Issue-7 2017. 
[13] A. Morgenshtein, A. Fish., I.A Wagner. “Gate Diffusion Input (GDI) – A Novel Power Efficient Method for Digital Circuits: A Design Methodology,” 14th ASIC/SOC Conference, Washington D.C., USA, pp. 39-43,2001. 
[14] P. Mishra ,A. Muttreja., and N.K Jha , “Low-power FinFET circuit synthesis using multiple supply and threshold voltages,” ACM J. Emerg. Tech. Comput. Syst., 5(2):1–23, Jul. 2009. 
[15] Po-Ming Lee, Chia-Hao Hsu, and Yun-Hsiun Hung, “Novel 10-T full adders realized by GDI structure,” in Proc. IEEE Int. Symp. On Integrated Circuits (ISIC-2007), pp. 115-118.