Reduced Test Pattern Generation using Reconfigurable Compression Techniques for Testing Soc

International Journal of Electronics and Communication Engineering
© 2015 by SSRG - IJECE Journal
Volume 2 Issue 3
Year of Publication : 2015
Authors : V.Vinothini and S.Yamuna
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How to Cite?

V.Vinothini and S.Yamuna, "Reduced Test Pattern Generation using Reconfigurable Compression Techniques for Testing Soc," SSRG International Journal of Electronics and Communication Engineering, vol. 2,  no. 3, pp. 29-33, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I3P120

Abstract:

This paper present a hybrid test vector compression method reducing the testing time and test data volume size of SOC. Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume size. Today the silicon densities increase day by day, so it become very difficultly to test SOC, because it need the large test pattern. The method consists of two steps: Burrow wheeler transform (BWT) and pattern overlapping method. BWT is a block sorting lossless and reversible data transform. It improves the efficiency of text compression algorithm. The hybrid based compression scheme provides the high compression ratio and fast testing time. The major contributions of this paper are as follows: 1) it develops an efficient pattern overlapping technique for test data in order to create maximum matching patterns. 2) it proposes a test compression technique using efficient pattern overlapping method to significantly reduce the testing time and memory requirements of SOC.

Keywords:

Automatic test equipment (ATE), Burrows– Wheeler transformation (BWT), designfor-testability (DFT), intellectual property (IP) core, system-on-chip (SoC) test, pattern overlapping method.

References:

[1] M. Abramovici, C. Stroud, and M. Emmert, “Using embedded FPGAs for SoC yield improvement,” in Proc. Des. Autom. Conf., 2002, pp. 713–724.
[2] K. Basu and P. Mishra, “Test data compression using efficient bitmask and dictionary selection methods,” IEEE Trans. VLSI Syst., vol. 18, no. 9, pp. 1277–1286, Sep. 2010.
[3] S. Biswas and S. R. Das, “A software-based method for test vector compression in testing system-on-a-chip,” in Proc. IEEE Instrumen. Meas. Technol. Conf., Apr. 2006, pp. 359–364.
[4] S. Biswas, S. R. Das, and E. M. Petriu, “Space compactor design in VLSI circuits based on graph theoretic concepts,” IEEE Trans. Instrumen. Meas., vol. 55, no. 4, pp. 1106–1118, Aug. 2006.
[5] M. Burrows and D. J. Wheeler, “A block-sorting lossless data compression algorithm,” Digit. Syst. Res. Center, Palo Alto, CA, USA, Tech. Rep. 124, 1994..
[6] A. El-Maleh, S. Al Zahir, and E. Khan, “Ageometric-primitives-based compression scheme for testing system-on-a-chip,” in Proc. VLSI Test Symp., 2001, pp. 54–58.
[7] V. Groza, R. Abielmona, and M. H. Assaf, “A self-reconīŦgurable platform for built-in self-test applications,” IEEE Trans. Instrumen. Meas., vol. 56, no. 4, pp. 1307–1315, Aug. 2007.
[8] M. Ishida, D. S. Ha, and T. Yamaguchi, “COMPACT: A hybrid method for compressing test data,” in Proc. VLSI Test Symp., 1998, pp. 62–69.
[9] V. Iyengar, K. Chakraborty, and B. T. Murray, “Built-in self testing of sequential circuits using precomputed test sets,” in Proc. VLSI Test Symp., 1998, pp. 418–423.
[10] A. Jas, J. G. Dastidar, and N. A. Touba, “Scan vector compres-sion/decompression using statistical coding,” in Proc. VLSI Test Symp., 1999, pp. 114–120.