A High Performance 128 to 2048-Point Pipeline SDF-FFT Architecture based on DPRAM for LTE and WiMAX Systems using Modified Low-Power Carry Select Adder
| International Journal of Electrical and Electronics Engineering |
| © 2026 by SSRG - IJEEE Journal |
| Volume 13 Issue 1 |
| Year of Publication : 2026 |
| Authors : Nancharaiah Vejendla, R. Ramana Reddy, N. Balaji |
10.14445/23488379/IJEEE-V13I1P101
How to Cite?
Nancharaiah Vejendla, R. Ramana Reddy, N. Balaji, "A High Performance 128 to 2048-Point Pipeline SDF-FFT Architecture based on DPRAM for LTE and WiMAX Systems using Modified Low-Power Carry Select Adder," SSRG International Journal of Electrical and Electronics Engineering, vol. 13, no. 1, pp. 1-10, 2026. Crossref, https://doi.org/10.14445/23488379/IJEEE-V13I1P101
Abstract:
Fast Fourier Transforms (FFTs) are essential in communications, signal processing, computer vision, measurements, and instrumentation. The time-domain signals are mapped into frequency-domain representations by FFT for the number of points specified. In telecommunications, FFT is widely used in Orthogonal Frequency Division Multiplexing (OFDM) to map various frequency components to perform the modulation and demodulation processes before transmission or reception. Owing to the high computational complexity, the FFT implementation for real-time applications is quite difficult. The FFT can be efficiently implemented in Field-Programmable Gate Array Logic (FPGA) for superior performance compared to embedded applications. This paper presents a Novel Semi-Pipelined FFT Architecture based on Single-Path Delay Feedback (SP-FFT-SPDT-DPRAM) with DP Random-Access Memory (RAM) for variable-point FFT. Using DP-RAM, the read and write operations for two locations can be performed instead of using single-port RAM. A low-power, low-area-based carry-select adder is utilized to minimize the power consumption and area in complex adders and multipliers. The projected design, implemented using 180 nm CMOS technology, demonstrates improved performance compared to existing architectures.
Keywords:
Discrete Fourier Transform (DFT), TFs (TF), Complex Number Multiplication, Fast Fourier Transform (FFT), Butterfly Structure. Single-path Delay Feedback (SDF), Semi-Pipelined Architecture, Processing Element (PE), and Digital Signal Processing (DSP).
References:
[1] Chu Yu et al., “A Low-Power 64-Point Pipeline FFT/IFFT Processor for OFDM Applications,” IEEE Transactions on Consumer Electronics, vol. 57, no. 1, pp. 40-40, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[2] M. Vinay Kumar, A. David Selvakumar, and P.M. Sobha, “Area and Frequency Optimized 1024 Point Radix-2 FFT Processor on FPGA,” 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Bengaluru, India, pp. 1-6, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Nooshin Mahdavi, R. Teymourzadeh, and Masuri Bin Othman, “VLSI Implementation of High Speed and High Resolution FFT Algorithm based on Radix 2 for DSP Application,” 2007 5th Student Conference on Research and Development, Selangor, Malaysia, pp. 1-4, 2007.
[CrossRef] [Google Scholar] [Publisher Link]
[4] Arathi Ajay, and R. Mary Lourde, “VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical Applications,” 2015 IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, pp. 68-73, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Hao Xiao et al., “VLSI Design of Low-Cost, High-Precision Fixed-Point Reconfigurable FFT Processors,” IET Computers and Digital Techniques, vol. 12, no. 3, pp. 105-110, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[6] Shaohan Liu, and Dake Liu, “A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 511-523, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Chu Yu, and Mao-Hsu Yen, “Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1793-1800, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Chu Yu, “A 128/512/1024/2048-Point Pipeline FFT/IFFT Architecture for Mobile WiMAX,” 2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE), Tokyo, Japan, pp. 243-244, 2013.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Harsha Keerthan Samudrala et al., “Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm,” 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Hyderabad, India, pp. 21-26, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Gyuseong Kang, Woong Choi, and Jongsun Park, “Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp. 3484-3494, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[11] S. Kala et al., “Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems,” 2014 Fifth International Symposium on Electronic System Design (ISED), Surathkal, Mangalore, India, pp. 20-24, 2014.
[CrossRef] [Google Scholar] [Publisher Link]