Randomized Verification of Ethernet

International Journal of VLSI & Signal Processing

© 2022 by SSRG - IJVSP Journal

Volume 9 Issue 2

Year of Publication : 2022

Authors : Dhyan V, Venu S, Syed Shabaz, Shaik Muinuddin, Madhura R

10.14445/23942584/IJVSP-V9I2P101

How to Cite?

Dhyan V, Venu S, Syed Shabaz, Shaik Muinuddin, Madhura R, "Randomized Verification of Ethernet," SSRG International Journal of VLSI & Signal Processing, vol. 9,  no. 2, pp. 1-4, 2022. Crossref, https://doi.org/10.14445/23942584/IJVSP-V9I2P101

Abstract:

CRC stands for cyclic redundancy check, a well-known error detection algorithm found in Ethernet, PCIe, etc. The Cyclic redundancy check (CRC) code is a simple but effective method for detecting errors during digital data transmission and storage. CRC implementation can use any hardware or software method. This application report introduces different software algorithms, comparing themselves according to memory and speed utilized. Various standard CRC codes will be used. Correction codes are a way of finding and correcting errors introduced by a transmission channel. Block and convolution codes are two important parts of a code. Both eliminate unwanted or redundant data by adding to message data the rating symbols. Even though correction techniques are not used here, they are post-response of CRC. Cyclic redundancy check (CRC) codes come under cyclic codes, which in turn come under linear block codes. Hardware and software program techniques can be used in CRC implementation; within the conventional hardware implementation, an easy shift signs up circuit plays the computations by dealing with the facts one bit at a time. Managing records as bytes or phrases in software program implementations becomes extra handy and faster. Verification of CRC is challenging; hence, it's been done using the system Verilog based on a standard verification methodology.

Keywords:

CRC, FPGA, PCIe, HWICAP.

References:

[1] Evgeniy Mytsko, Andrey Malchukov, Valeriy Kim, Alexander Osokin, Ivan Zoev, Svetlana Ryzova," Software Implementation Research of Crc Computation Algorithms Compatible With Pkzip, Winrar, Ethernet.”
[2] Philip Koopman," 32-Bit Cyclic Redundancy Codes for Internet Applications"
[3] Vinaya R Gad, Rajendra S Gad, Gourish M Naik, "Configurable Crc Error Detection Model for Performance Analysis of Polynomial: Case Study for the 32-Bits Ethernet Protocol."
[4] Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Larsson-Edefors, Dake Liu,“ Vlsi Implementation of Crc-32 for 10 Gigabit Ethernet.”
[5] Huan Liu, Zhiliang Qiu, Weitao Pan, Jun Li, Ling Zheng and Ya Gao "Low- Cost and Programmable Crc Implementation Based on Fpga" Ieee Transactions on Circuits and Systems—Ii: Express Briefs, vol. 68, no. 1, 2021.
[6] Cyclic Redundancy Check Computation By Patrick Geremia. (Online) Available: Https://Documents.Pub/Document/Cyclic-Redundancy-Check-Computation-An-Implementation-Redundancy-Check-Computation.Html
[7] M. E. Kounavis and F. L. Berry, "Novel Table Lookup-Based Algorithms for High-Performance Crc Generation," Ieee Trans. Comput., vol. 57, no. 11, pp. 1550–1560, 2008. 
[8] A. Akagic and H. Amano, "High-Speed Fully-Adaptable Crc Accelerators,"Ieice Trans. Inf. Syst., vol. 96, no. 6, pp. 1299-1308, 2013.
[9] L. Kekely, J. Cabal, and J. Koˇrenek, "Effective Fpga Architecture for GeneralCrc," in Proc. Int. Conf. Archit. Comput. Syst., pp. 211–223, 2019.
[10] C. Toal, K. Mclaughlin, S. Sezer, and X. Yang, "Design and Implementationof a Field-Programmable Crc Circuit Architecture," Ieee Trans. Very Large Scale Integr. (Vlsi) Syst., vol. 17, no. 8, pp. 1142–1147, 2009.
[11] the P4 Language Specification, Version 1.0.5, P4 Lang. the Consortium, Stanford,Ca, Usa, 2018.
[12] M. Grymel and S. B. Furber, "A Novel Programmable Parallel Crc Circuit," Ieee Trans. Very Large Scale Integr. (Vlsi) Syst., vol. 19, no. 10, pp. 1898–1902, 2011.
[13] S. Gueron, "Speeding Up Crc32c Computations With Intel Crc32Instruction," Inf. Process. Lett., vol. 112, no. 5, pp. 179–185, 2012.
[14] G. Campobello, G. Patane, and M. Russo, “Parallel Crc Realization,” Ieee Trans. Comput., vol. 52, no. 10, pp. 1312–1319, 2003.
[15] H. Liu, Z. Qiu, W. Pan, J. Li, L. Zheng, and Y. Gao, “Low-Cost and Programmable Crc Implementation Based on Fpga,” 2020.
[16] K. Vipin and S. A. Fahmy, "Fpga Dynamic and Partial Reconfiguration: A Survey of Architectures Methods and Applications," Acm Comput. Surveys, vol. 51, no. 4, pp. 1–39, 2018.
[17] P. Orosz, T. Tóthfalusi, and P. Varga, "Fpga-Assisted Dpi Systems: 100 Gbit/S and Beyond," Ieee Commun. Surveys Tuts., vol. 21, no. 2, pp. 2015– 2040, 2019.
[18] M. Jubin and T. Nayak, "Reconfigurable Very High Throughput Low Latency Vlsi (Fpga) Design Architecture of Crc 32," Integration, vol. 56, pp. 1–14, 2017