Analysis of Low-Power and Area-Efficient Shift Registers using Pulsed Latch

International Journal of Electronics and Communication Engineering

© 2016 by SSRG - IJECE Journal

Volume 3 Issue 1

Year of Publication : 2016

Authors : P. Rahul Reddy

10.14445/23488549/IJECE-V3I1P102

How to Cite?

P. Rahul Reddy, "Analysis of Low-Power and Area-Efficient Shift Registers using Pulsed Latch," SSRG International Journal of Electronics and Communication Engineering, vol. 3,  no. 1, pp. 1-4, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I1P102

Abstract:

Flip-flops is perilous timing elements in digital circuits which have a huge influence on the circuit speed and power consumption. The performance of flip-flop is an significant element to regulate the efficiency of the entire synchronous circuit.This paper recommends a low-power and area-efficient shift register using pulsed latches. Therefore area and power consumption are reduced by substituting flip-flops with pulsed latches. This technique explains the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals as an alternative of the conventional single pulsed clock signal. Also the shift register uses a small number of the pulsed clock signals by grouping the latches to more than a few sub shifter registers and using supplementary temporary storage latches.

Keywords:

Area-efficient, flip-flop, pulsed clock, pulsed latch, shift register.

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