Implementation of low power wireless sensor node with fault tolerance mechanism

International Journal of Electronics and Communication Engineering
© 2016 by SSRG - IJECE Journal
Volume 3 Issue 4
Year of Publication : 2016
Authors : R.Divyasharon and Dr.D.Sridharan
How to Cite?

R.Divyasharon and Dr.D.Sridharan, "Implementation of low power wireless sensor node with fault tolerance mechanism," SSRG International Journal of Electronics and Communication Engineering, vol. 3,  no. 4, pp. 1-5, 2016. Crossref,


Wireless Sensor Network based solutions have been widely used since it has the potential to increase our ability to monitor and interact with our environment. WSN consist of number of wireless sensor nodes. Therefore, a node should have long time operating capability and efficient energy management. WSN are usually affected by noise which degrades the performance. It may be affected either by random error or burst error. In this paper, a low power sensor node with fault tolerance capability is developed using verilog code. Hamming code and Cyclic Redundancy Check is used for error free communication. The main aim of this project is to implement the design in FPGA because of its reprogramming ability and the power efficiency can be improved significantly in comparison with commercially micro-controller based sensor.


Low power sensor node, verilog, hamming code, cyclic redundancy check, VLSI, FPGA.


[1] J.Bag, S.Roy, S.K.Sarkar, “Realization of a low power sensor node processor for Wireless Sensor Network and its VLSI implementation” IEEE international Advance computing conference, 2014,pp.101-105.
[2] F. Akyildiz, W. Su, Y. Sandarasurbramaniam, E. Cayirci, “Wireless sensor networks: a survey” Computer Networks Journal, Elsevier vol. 38 no. 4. pp. 393-422. 2002.
[3] Renyan Zhou, Leibo Liu, Shouyi Yin, Ao Luo, Xinkai Chen, Shaojun Wei, “ A VLSI Design of Sensor Node for Wireless Image”, IEEE, pp. 149-152. 2010
[4] Aki Hopponen, “Low power design for Wireless Sensor Networks” Springer, 2012.
[5] G. Lu, N. Sadagopan, B. Krishnamachari and A. Goel. “Delay efficient sleep scheduling in Wireless sensor networks'” in Proc. of IEEE INFOCOM, 2005, vol. 4, pp 24702481.
[6] G. U. Gamm, M, Kostic, M. Sippel and L. M. Reindl, “Lowpower sensor node with addressable wake-up on-demand capability” Int. Journal of Sensor Networks, Inderscience, Vol. ll, No. l, pp. 49-56. 2012
[7] Pranjali Pothare, Prajakta Ambatkar, “Hamming code for single bit error detection & error correction with even parity using VHDL” International Journal of Advanced Research in Computer Engineering & Technology, Volume 4 Issue 1, January 2015
[8] Rajesh Kumar Gupta , Prof. Rajeshwar Lal Dua , “30 BIT Hamming Code for Error Detection and Correction with Even Parity and Odd Parity Check Method by using VHDL” International Journal of Computer Applications (0975 – 8887),Volume 35– No.13, December 2011.
[9] S. Shukla , N. W. Bergmann , “Single bit error correction implementation in CRC-16 on FPGA”IEEE conference on fieldprogrammable technology, 2014,pp.319-322.
[10] B.Sakthivel, P.Nagarajan, B.Sivananthan, “Detection and prevention of congestion attacks Using Multivariate Correlation Analysis”, SSRG International Journal of Computer Science and Engineering (SSRG-IJCSE), volume1 issue9, Nov 2014.
[11] Sirisha D, B Venkateswaramma, M Srikanth and A Anil Babu , “Wireless Sensor Based Remote Controlled Agriculture Monitoring System Using ZigBee” , SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE ),volume 2 Issue 4 April 2015.
[12] Harshada L. Borkar, V.N. Bhonge, “Design And Implementation Of Reed Solomon Encoder And Decoder”,SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) , volume 2 issue 1 Jan 2015