An Analysis of Device Characteristics of Strained N-Channel MOSFET
|International Journal of Electronics and Communication Engineering|
|© 2016 by SSRG - IJECE Journal|
|Volume 3 Issue 8|
|Year of Publication : 2016|
|Authors : Shivam Sharma, Rahul Pandey, Aditya Pundir, Vijendra Kumar Patel and Nishant Kumar Agrawal|
How to Cite?
Shivam Sharma, Rahul Pandey, Aditya Pundir, Vijendra Kumar Patel and Nishant Kumar Agrawal, "An Analysis of Device Characteristics of Strained N-Channel MOSFET," SSRG International Journal of Electronics and Communication Engineering, vol. 3, no. 8, pp. 14-17, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I8P122
Large effects of strain on the electrical resistance of silicon were exposed not long after the recognition of silicon as the material for the growth of solid state electronics. As we are approaching to Nano scale, the CMOS applications, device dimensions are getting their scaling limit and it is affecting the gate leakage current, drain induced barrier lowering (DIBL) etc. to a rise. It also worsening the required characteristics and performance of the devices. To overcome this some significant changes in device structures and materials will be needed for continued transistor miniaturization and equivalent performance improvements. This paper is a comparison of performances of unstrained MOSFET with performances of n-channel planer MOSFET with introduction of strain into it, for different channel lengths and its simulation with ATLAS, a 2D device simulator from Silvaco Inc.
Nano scale strained-Si/SiGe MOSFET, short channeleffects, simulation, threshold voltage, DIBL, CMOS etc.
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