Ethernet MAC Verification with Loopback Mechanism using Efficient Verification Methodology

International Journal of Electronics and Communication Engineering
© 2016 by SSRG - IJECE Journal
Volume 3 Issue 11
Year of Publication : 2016
Authors : Sridevi Chitti, P Chandrasekhar and M Asharani
How to Cite?

Sridevi Chitti, P Chandrasekhar and M Asharani, "Ethernet MAC Verification with Loopback Mechanism using Efficient Verification Methodology," SSRG International Journal of Electronics and Communication Engineering, vol. 3,  no. 11, pp. 16-19, 2016. Crossref,


This paper describes Efficient Verification Methodology (EVM) based constrained random verification (CRV) of a SoC. SoC taken into consideration is Ethernet MAC module with loopback mechanism using XGMII interface. The environment of verification, which is created by means of efficient verification methodology for system verilog is scalable, predictable and reusable and can reduce verification time. Using this verification environment, existence of bugs in the design can be found and design errors with corner cases can be easily located by the help of constraints


Efficient verification methodology, MAC, Verification IP, constrained random verification, Gigabit Ethernet, XGMII.


[1] Young-Nam Yun;, “Beyond UVM for practical SoC verification”, SoC Design Conference (ISOCC), 2011 International, pp158-162, 2011.
[2] Creating a reusable testbench using cadance’s testbuilder and AMBA TVM Prakash Rashinkar, Peter Paterson and Leena Singh, SYSTEM-ON-A-CHIP VERIFICATION Boston: Kluwer Academic Publishers, 2001. 
[3] MV Lau,, S. Shieh, Pei-Feng Wang, B. Smith, D. Lee, J. Chao, B. Shung, and Cheng-Chung Shih, "Gigabit ethernet switches using a shared buffer architecture,"Communications Magazine, IEEE, vol. 41, no. 12, pp. 76 - 84, dec. 2003. 
[4] Assaf, M.H, Arima ; Das, S.R. ; Hernias, W, Petriu, E.M, “Verification of Ethernet IP Core MAC Design Using Deterministic Test Methodology”, IEEE International instrumentation and Mesurements Technology Conference, doi.10.1109/IMTC.2008.4547312, victoria, May 2008. 
[5] Tonfat, J, Reis, R, “Design and Verification of a layer-2 Ethernet MAC classification Engine for a gGigabit Ethernet Switch”, Proc IEEE  Electronics, Circuits, and Systems doi. 10.1109/ICECS.2010.5724475, Athens, Dec 2010. 
[6] Frazier,H. “The 802.3z gigabit Ethernet Standard”, Proc IEEE J, doi10.1109/65.690946, vol-12, May-June 1998. 
[7] H. D. Foster, A. Krolnik, and D. Lacey, “Assertion-Based Design,” 2nded., Kluwer Academic Publishers, 2004. 
[8] J. Bergeron, E. Cerny, A. Hunter, A. Nightingale, “Verification Methodology Manual for SystemVerilog,” Springer Publisher, Sep 1, 2005, pp. 260-282. 
[9] Accellera, UVM 1.1 Reference Manual, Jun. 2011 
[10] Accellera, UVM 1.1 User Guide, May. 2012. 
[11] J. Cho, S. Choi, S.-I. Chae, “Constrained-Random Bitstream Generation for H.264/AVC  Decoder Conformance Test,” IEEE Trans. on Consumer Electronics, vol. 56, no. 2, pp.  848-855, May. 2010.