Schematic Design and Layout of Flipflop using CMOS Technology

International Journal of Electronics and Communication Engineering
© 2017 by SSRG - IJECE Journal
Volume 4 Issue 7
Year of Publication : 2017
Authors : Sana Ur Rahman and Tarana Afrin Chandel
How to Cite?

Sana Ur Rahman and Tarana Afrin Chandel, "Schematic Design and Layout of Flipflop using CMOS Technology," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 7, pp. 16-18, 2017. Crossref,


 In this paper the work is done on low power and high speed design of flipflop using CMOS technology on different nanoscale technologies i.e. 90 nm, 65nm and 45 nm. The transistor used small area and low power consumption. By decreasing the geometrical feature size of the transistors we can achieve the low power consumption and high speed of integrated circuit in VLSI design. When the technology size decreases in the result of this the leakage power increases which is reduced by type of CMOS technology. The comparisons are held TSPC D-Flipflop and Multi threshold CMOS technology and among the power consumption propagation delay and power dissipation product. The work is carried out with the help of tanner EDA tool.


CMOS technology, Nanoscale technology, VLSI design, Tanner EDA tool.


[1] CH. DayaSagar and T. Krishna Moorthy, “Design of A Low Power FlipFlop using MTCMOS”International Journal of Computer Applications & information Technology in July 2012.
[2] Rishikesh V. Tambat*and SonalA.LakhotiyaȦ, “Design of Flip-Flops for High Performance VLSI Applications using Deep Submicron CMOS Technology”International Journal of Current Engineering and Technology in April 2014.
[3] B.Chinnarao, B.Francis & Y.Apparao,”Design of A Low Power Flip-Flop Using CMOS Deep Submicron Technology” Intrnational Journal of Electronics Signals and Systems in 2012.
[4] Pratiksha Gupta, Dr. Rajesh Mehra,”Low Power Design of SRFlipFlop Using 45nm Technology” IOSR Journal of VLSI and Signal Processing in 2016.
[5] K.Rajasri, A.Bharathi, M.Manikandan, ”Performance of FlipFlop using 22nm CMOS Technology” International Journal of Innovative Research in Computer and Communication Engineering in 2014.
[6] Kaphungkui N K ,”Design of low-power, high performance flip-flops” International Journal of Applied Sciences and Engineering Research in 2014.
[7]M. A. Hernandez and M. L. Aranda, “A Clock Gated Pulse – Triggered D Flip-Flop For Low Power High Performance VLSI Synchronous Systems,” Proceedings of the 6th International Caribben Conference on devices, circuits and systems, Mexico, Apr. 26-28, 2006.
[8]J.S. Wang, P.H. Yang “A Pulse Triggered TSPC FF for high speed, low power VLSI design applications” IEEE, 1998
[9]J. Wang et al., "Design of a 3-V 300-MHz Low-Power 8-b ×8-b Pipelined Multiplier Using Pulse-Triggered TSPC Flip Flops," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 583-591, Apr. 2000.
[10] A. Keshavarzi, K. Roy, and C. F. Hawkins, “Intrinsic leakage in low power deep submicron CMOS ics,” in Proc. Int. Test Conf., pp. 146– 155, 1997.