Minimization of Power for the Design of an Optimal Flip Flop

International Journal of Electronics and Communication Engineering
© 2017 by SSRG - IJECE Journal
Volume 4 Issue 7
Year of Publication : 2017
Authors : Kahkashan Ali and Tarana Afrin Chandel
How to Cite?

Kahkashan Ali and Tarana Afrin Chandel, "Minimization of Power for the Design of an Optimal Flip Flop," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 7, pp. 19-25, 2017. Crossref,


The power consumption is critically the most important factor in the modern VLSI circuits especially for those circuits which work on low-power applications. This designing aims in achieving optimum speed performance for low power and low noise simultaneously. In this paper basically we are dealing with the power minimization factor. In modern VLSI circuits power saving plays the vital role especially for the applications which runs on low power such as latches, flip-flops and also some logic components which plays a vital role in the functioning of digital system. The main factor is to reduce the power loss in both the flip-flops and clock distribution networks. In this paper we have made a comparison in terms of power loss, parasitic values and no. of transistors in some of the existing classes of the flipflop. Each flip-flop have been analysed and the output is simulated using Tanner EDA tool in 180nm technology. The comparison made shows the best result between the working design of the flip-flop and the existing flip-flop designs.


Tanner EDA, clock distribution networks, Flip flops and Power minimization, pulse triggered.


[1]Priya Jose, “An Optimal Flip Flop Design For VLSI Power Minimization,” IJAET, vol.7 no. 1, pp. 274-282, Mar. 2014
[2] Venkateswarlu. Padidapu, Paritala. Aditya RatnaChowdary, Kalli Siva Nagi Reddy, “Pulse Triggered Flip-Flops Power Optimization Techniques for Future Deep Sub Micron Applications,” IJETT, vol.4, no. 9, Sept. 2013
[3]. H. Kojima, S. Tanaka, and K. Sasaki, “Half-swing clocking scheme for 75% power saving in clocking circuitry,” IEEE J. Solid- State Circuits, vol. 30, pp. 432– 435, Apr. 1995.
[4]. N. Nedovic, M. Aleksic, and V. G. Oklobdzija“Conditional precharge techniques for power-efficient dual-edge clocking,” in Proc. Int. Symp.Low-Power Electron. Design, Monterey, CA, Aug. 12- 14, 2002, pp. 56-59.
[5]. B. S. Kong, S. S. Kim, Y. H. Jun, "Conditional Capture Flip- Flop Technique for Statistical Power Reduction", Digest of Technical Papers, p290-291, February 2000.
[6].B. Nikolic, V. G. Oklobdzija, V. Stajanovic, W. Jia, J. K. Chiu, and M. M. Leung, “Improved sense-amplifier based flip-flop: Design and measurements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876–883, Jun. 2000.Circuits and Systems, IEEETransactions on, vol. 26, no. 2, pp. 203 –215, Feb. 2007.
[7]. B. Voss and M. Glesner, “A lowpower sinusoidal clock” Proc. IEEE Int. Symp. Circuits Syst., May 2001, vol. 4, pp. 108–111.
[8]. P. Zhao, T. Darwish, and M. Bayoumi, “High-performance and low power conditional discharge flip-flop,” IEEE Trans. Very Large Scale Integrated. (VLSI) Syst., vol. 12, no. 5, pp. 477-484, May 2004.
[9]. B. Kong, S. Kim, and Y. Jun, “Conditional-capture flip-flop for statistical power reduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp.1263-1271, Aug. 2001.
[10] H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, “Ultra low power clocking scheme using energy recovery and clock gating,” IEEE Trans. Very Large Scale Integrated. (VLSI) Syst., vol. 17, pp. 33–44, Jan 2009.
[11] Yin-Tsung Hwang, Jin-Fa Lin, and Ming-Hwa Sheu, “Low- Power Pulse-Triggered Flip-Flop Design with Conditional Pulse Enhancement Scheme”,vol.20,no 2.feb 2012.
[12].C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, “Conditional data mapping flip-flopsfor low-power and high-performance systems,” IEEE Trans. Very Large Scale Integrated (VLSI) Systems, vol. 14, pp. 1379-1383, Dec. 2006
[13].Q. Wu, M. Pedram, and X. Wu, “Clock-gating and its application to low power design of sequential circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 47, no. 3, pp. 415–420, Mar. 2000.