Fault Tolerant Parallel Filter in Digital Communication Systems
|International Journal of Electronics and Communication Engineering|
|© 2017 by SSRG - IJECE Journal|
|Volume 4 Issue 9|
|Year of Publication : 2017|
|Authors : Jyotishma Bharti and Tarana Afrin Chandel|
How to Cite?
Jyotishma Bharti and Tarana Afrin Chandel, "Fault Tolerant Parallel Filter in Digital Communication Systems," SSRG International Journal of Electronics and Communication Engineering, vol. 4, no. 9, pp. 1-3, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I9P101
There are various types of filters are used by Digital signal processing (DSP) applications. In which digital parallel FIR filters are very widely used in numerous application. Over the years, many implementation techniques of digital FIR filter for DSP application has exploited the various practical difficulties such as low speed, high delay and above of all fault tolerance. Due to the VLSI complexity scaling, there are many complex systems that embed with many filters. The filters operations in those complex systems are usually parallel. As filters are the unit that comes in any type of communication system ranging from simple voice data to complex real-time data conversation. So it is then mandatory to implement some technique that shows the fault tolerance achieved in parallel filters. In this paper, we are going through various ideas that show that parallel filters can be protected using error correction codes (ECCs).
Error Correction Codes (ECC), Digital Signal Processing (DSP), Finite Impulse Response (FIR) Parallel FIR, Very Large Scale Integration (VLSI).
 P. P. Vaidyanathan, Multirate Systems and Filter Banks, Englewood Cliffs, N.J., USA: Prentice Hall, 1993.
 A. Sibille, C. Oestges and A. Zanella, MIMO: From Theory to Implementation, New York, NY, USA: Academic, 2010.
 N. Kanekawa, E. H. Ibe, T. Suga, and Y. Uematsu, Dependability in Electronic Systems: Mitigation of Hardware Failures, Soft Errors, and ElectroMagnetic Disturbances, New York, NY, USA: Springer-Verlag, 2010.
 M. Nicolaidis, “Design for soft error mitigation,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 405–418, Sep. 2005.
 C. L. Chen and M. Y. Hsiao, “Error-correcting codes for semiconductor memory applications: A state-of-the-art review,” IBM J. Res. Develop.vol. 28, no. 2, pp. 124–134, Mar. 1984.
 A. Reddy and P. Banerjee “Algorithm-based fault detection for signal processing applications,” IEEE Trans. Comput., vol. 39, no. 10, pp. 1304– 1308, Oct. 1990.
 T. Hitana and A. K. Deb, “Bridging concurrent and non-concurrent error detection in FIR filters,” in Proc. Norchip Conf., 2004, pp. 75–78.
 Y.-H. Huang, “High-efficiency soft-error tolerant digital signal processing using fine grain sub word-detection processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 291–304, Feb. 2010.
 Yu-Chi Tsao and Ken Choi, 2012. “Area- Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm” IEEE transactions on very large scale integration (VLSI) Systems, vol. 20, no. 2, Feb. 2012.
 Yu-Chi Tsao and Ken Choi, 2011. “Hardware- Efficient Parallel FIR Digital FilterStructures For Symmetric Convolutions “978-1-4244-9474- 3/11/$26.00 ©2011 IEEE.
 Lavina Magdalene Mary “Area Efficient Parallel Fir Digital Filter Structures Based On Fast Fir Algorithm” Vol. 3, Issue 1, January –February 2013, pp.2042-2046
 D. A. Parker and K. K. Parhi, 1997. “Low area/ power parallel FIR digital filter implementations,” J. VLSI Signal Process.Syst., vol. 17, no. 1, pp. 75–92, 1997.
K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation.New York: Wiley, 1999.
J. G. Chung and K. K. Parhi, 2002. “Frequency spectrum- based low-area low-power parallel FIR filter design,” EURASIP J. Appl. Signal Process., vol. 2002, no. 9, pp. 444–453, 2002.
Alfredo Rosado-Muñoz and Manuel Bataller- Mompeán,“FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches," vol.58, no.3, Mar.2011.
 Z.-J. Mou and P. Duhamel, 1991. “Short-length FIR filters and their use in fast nonrecursive filtering,” IEEE Trans. Signal Process., vol. 39, no.6, pp. 1322–1332, Jun. 1991.
 C. Cheng and K. K. Parhi, 2004. “Hardware-efficient fast parallel FIR filter structures based on iterated short Convolution," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 8, pp. 1492–1500, Aug. 2004.
 C. Cheng and K. K. Parhi, 2005. “Further complexity reduction of parallel FIR filters,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2005), Kobe, Japan, May 2005.