Different parameter analysis for SRAM
|International Journal of Electronics and Communication Engineering|
|© 2019 by SSRG - IJECE Journal|
|Volume 6 Issue 12|
|Year of Publication : 2019|
|Authors : Vartika Pandey, Manisha Pattaniak, R K Tiwari|
How to Cite?
Vartika Pandey, Manisha Pattaniak, R K Tiwari, "Different parameter analysis for SRAM," SSRG International Journal of Electronics and Communication Engineering, vol. 6, no. 12, pp. 3-8, 2019. Crossref, https://doi.org/10.14445/23488549/IJECE-V6I12P102
In today’s VLSI design circumstances, upscaling of technology and downscaling of transistors are inversely proportional. Power dissipation impactsSRAM cells widely as the technology shrinks down. Static Random Access Memory (SRAM) is designed to interface with CPU directly, DSP processors, μprocessors, and low-power applications such as handheld devices with long battery life. In the total power consumption, leakage and other parameters also play an important role in the circuit’s performance. In this paper, we have applied two diverse technologies on 6 T SRAM, and the result has been comparedwith6T SRAM formed with memristor.
SRAM, DTMOS, Memristor, Sleep transistor
 Ambika Prasad Shah, NandakishorYadav, Ankur Beohar, and Santosh Kumar Vishvakarma, “On-chip Adaptive Body Bias for Reducing the impact of NBTI on 6T SRAM Cells”, vol. 31.no 2,pp 242-249, 2018
 A. Calimera, M. Loghi, E. Macii, and M. Poncino, “Dynamic Indexing: Leakage-aging co-optimization for caches,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 2, pp. 251–264, 2014.
 M. Wirnshofer, Variation-Aware Adaptive Voltage Scaling for DigitalCMOS Circuits, Springer Series in Advanced Microelectronics, Springer,2013.
 Y. Wang, M. Enachescu, S. D. Cotofana, and L. Fang, “Variationtolerant on-chip degradation sensors for dynamic reliability management systems, Microelectronics Reliability vol. 52, no. 9, pp. 1787–1791, 2012.
 G. D. Panagopoulos and K. Roy, “A three-dimensional physical model for Vth variations considering the combined effect of NBTI and RDF,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2337–2346,
 Paramita Chowdhury, Kuheli Dutta, and Sunipa Roy, A new Gated –Ground- Sleep Architecture for Ultra-Low Leakage of SRAM cell”, Emerging Trends in Electronic Devices and Computational Techniques (EDCT)2018, Kolkata
 L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight, R.H. Dennard, R.K.Montoye, L. Sekaric, S.J. McNab, A.W. Topol, C.D. Adams, K.W.Guarini, and W. Haensch, “Stable SRAM cell design for the 32 nm node and beyond” Symposium on VLSI Technology, June 2005, pp. 128–129.
 Yiming Li, Shao-Ming Yu, Jiunn-Ren Hwang, and Fu-Liang Yang, “Discrete Dopant Fluctuations in 20-nm/15-nm-Gate Planar CMOS”, vol55, no 6, June 2008, pp. 1449 – 1455
 LEON 0. CHUA, “Memristor-The Missing Circuit Element,” IEEE Transactions on Circuit Theory, Vol.18, pp. 507–519, September 1971,
 L. Chua and S. M. Kang, “Memristive devices and systems,” Proc. IEEE, vol. 64, pp. 209–223, Feb 1976.
 Lin, Yong-Bin Kim, and Fabrizio Lombardi, “Design and Analysis of a 32nm PVT Tolerant CMOS SRAM Cell for Low Leakage and HIGHStability”, Elsevier, vol. 43, no. 2, pp. 176–187, 2010
 Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, AvinoamKolodny, and Uri C. Weiser, “Memristor-Based Material Implication (IMPLY)Logic: Design Principles and Methodologies,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 22, NO. 10, October 2014
 B.H. Calhoun, Yu Cao, Xin Li, Ken Mai, L.T. Pileggi, R.A. Rutenbar, and K.L. Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS,” Proceedings of the IEEE, vol. 96, pp. 343–365, February 2008
 J.P. Kulkarni, K. Kim, and K. Roy, “A 160 mV robust Schmitt trigger based subthreshold SRAM”, IEEE Journal of Solid-State Circuits, vol.42, pp.2303–2313, 2007
 B.H. Calhoun, andA.P. Chandrakasan, “A 256 kb 65 nm sub-thresholdSRAM design for ultra-low-voltage operation”, IEEE Journal of Solid-State Circuits vol.42, pp. 680–688, 2007
 K. Ragini, Dr. M. Satyam, and Dr. B.C. Jinga, “Variable threshold approach (through dynamic threshold MOSFET)
for the universal logic gate,” VLSICS; vol. I, No. I, March 2010.
 L. O. Chua, “Memristor – the Missing Circuit Element,” IEEE Transactions on Circuit Theory, Vol. 18, No. 5, pp.507-519, 1971
 V. Niranjan andManeesha Gupta, “An Analytical Model of the BulkDTMOS transistor,” Journal of Electron Devices; Vol.8; pp. 329-338,2010
 Rakesh Gupta.Article: Design of a Low Voltage Class-AB CMOS Super Buffer Amplifier with Sub Threshold and Leakage Control, International Journal of Engineering Trends and Technology (IJETT), V7(1):13-17; January 2014
 Sourabh Sethi “Memristor Model Based on Generalized Boundary Condition,” International Journal of Engineering Trends and Technology (IJETT), V49(4),192-194 July 2017. ISSN:2231-5381
 M. Nizamuudin “Simulation study of CMOS based 6 Transistors SRAM”, International Journal of Engineering Trends and Technology (IJETT), V44(5),218-220 February 2017. ISSN:2231-5381
 Garima Upadhyay, Amit Singh Rajput, Nikhil Saxena “A drowsy cache method based 6T SRAM cell with different performance parameter at 32 nm Technology”, International Journal of Engineering Trends and Technology (IJETT), V42(8),411-415 December 2016. ISSN:2231-5381
 Pankaj Agarwal, Nikhil Saxena, Nikhita Tripathi. “Low Power Design and Simulation of 7T SRAM Cell using various Circuit Techniques”. International Journal of Engineering Trends and Technology (IJETT). V4(5):1688-1693 May 2013. ISSN:2231-5381
 Anitha. K, Darwin.S, Mangala MariSelvi.E, Vijayalakshmi. K” Design and Simulation of SRAM to Reduce Leakage Current using Enhanced Galeor Approach,” International Journal of Engineering Trends and Technology (IJETT), V32(7),338-342 February 2016. ISSN:2231-538