A Review of Leakage Power Reduction Techniques for VLSI Applications
|International Journal of Electronics and Communication Engineering|
|© 2021 by SSRG - IJECE Journal|
|Volume 8 Issue 2|
|Year of Publication : 2021|
|Authors : Shruti Hathwalia, Dr.Naresh Grover|
How to Cite?
Shruti Hathwalia, Dr.Naresh Grover, "A Review of Leakage Power Reduction Techniques for VLSI Applications," SSRG International Journal of Electronics and Communication Engineering, vol. 8, no. 2, pp. 1-5, 2021. Crossref, https://doi.org/10.14445/23488549/IJECE-V8I2P101
Power dissipation has become one of the VLSI circuit structure's significant worries with the fast launching of battery worked applications. In high-performance structures, the leakage segments of power consumption are equivalent to the switching segment. This will keep incrementing with innovation scaling, except if effective procedures are introduced for controlling the leakage. This paper gives a thorough report, examination, and correlation of leakage power reduction systems and techniques. Additionally, the advantages and disadvantages of different strategies for decreasing leakage power are introduced. These methods can be stretched out to any complex advanced digital implementation.
Leakage/ Spillage Power reduction, CMOS circuits, Leakage/Spillage current, MTCMOS
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