Implementation of A DRAM 4×4 (Dynamic Random Access Memory) With Self Controllable Voltage Level (SVL) Technique
|International Journal of Electronics and Communication Engineering|
|© 2014 by SSRG - IJECE Journal|
|Volume 1 Issue 10|
|Year of Publication : 2014|
|Authors : S Md Sameer and K Sanjeeva Rao|
How to Cite?
S Md Sameer and K Sanjeeva Rao, "Implementation of A DRAM 4×4 (Dynamic Random Access Memory) With Self Controllable Voltage Level (SVL) Technique," SSRG International Journal of Electronics and Communication Engineering, vol. 1, no. 10, pp. 23-27, 2014. Crossref, https://doi.org/10.14445/23488549/IJECE-V1I10P108
Today trend is circuit characterized by responsibility, low power dissipation, low discharge current, low price and there's needed to scale back every of those. to scale back device size and increasing chip density have increase the planning quality. The recollections have provided the system designer with elements of right smart capability and in depth application. Dynamic random access memory (DRAM) offers the advantage for high-density knowledge storage. DRAM essentially a memory array with individual bit access refers to memory with each browse and Write capabilities. Here 3T DRAM is implementing with self manageable voltage level (svl) technique is for reducing discharge current in zero.12um technology. The simulation is completed by victimization micro wind three.1 & dsch2 and offers the advantage of reducing the discharge current up to fifty seven.
low leakage power, high performance, self controllable voltage level technique, low cost, low power.
 W. K. Luk And R. H. Dennard, “A Novel Dynamic Memory Cell With Internal Voltage Gain,” Ieee Journal Of Solid-State Circuits, Vol. 40, No. 4, April 2005.
 H. J. Yoo, “A Low Voltage High Speed Self-Timed Cmos Logic For The Multi-Gigabit Synchronous Dram Application,” Ieice Trans. Electron., Vol. E80-C, No. 8, Pp. 1126–1128, Aug. 1997..
 John E. Leiss, Pallab K. Chatterjee, And Thomas C. Holloway, ” Dram Design Using The Taper-Isolated Dynamic Ram Cell,‟‟ Ieee Transactions On Electron Devices, Vol. Ed-29, No. 4, April 1982.
 G. W. Taylor, P. K. Chatterjee, H-S. Fu, And A. F.Tasch, Jr., “A Punch-Through Isolated Ram Cell,” In IeeeIedm Tech. Dig., P. 352, 1978.
 K. M. Cao, W. –C. Lee, W. Liu, X. Jin, P. Su, S.K. Fung, J. X. An, B. Yu, C. Hu, “Bsim4 Gate Leakage Model Including Source-Drain Partition,” Iedm Meeting 2000, Iedm Technical Digest, Pp. 815-818, December, 2000.
 R. X. Gu, And M. I. Elmasry, “Power Dissipation Analysis And Optimization For Deep Submicron Cmos Digital Circuits,” IeeeJssc, 31(5):707–713, May 1996.
 Y. TaurAnd T. H. Ning, “Fundamentals Of Modern Vlsi Devices,” (1998), Pp 200-202.
 N. H. E. Weste, And K. Eshraghian, Editor. “Principles OfCmosVlsi Design”, A Systems Perspective, 2nd Ed. Addison-Wesley, 1993.
 Fumiyoshi Matsuoka, Hiroshi Sakuraba, Member, Ieee, And FujioMasuoka, Fellow, Ieee, “Device Design Guidelines For Fc-Sgt Dram Cells With High Soft-Error Immunity,” Ieee Transactions On Electron Devices, Vol. 52, No. 6, June 2005.