Review: Design and Implementation of Reed Solomon Encoder and Decoder
| International Journal of Electronics and Communication Engineering |
| © 2015 by SSRG - IJECE Journal |
| Volume 2 Issue 1 |
| Year of Publication : 2015 |
| Authors : Harshada l. Borkar and prof. V.n. Bhonge |
10.14445/23488549/IJECE-V2I1P107
How to Cite?
Harshada l. Borkar and prof. V.n. Bhonge, "Review: Design and Implementation of Reed Solomon Encoder and Decoder," SSRG International Journal of Electronics and Communication Engineering, vol. 2, no. 1, pp. 14-18, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I1P107
Abstract:
This paper presents a literature survey related to Reed Solomon encoder and decoder. In this project fast encoding and decoding algorithm using Reed Solomon codes is developed for the processing of self correcting logic in erroneous condition which is widely used in numerous applications. The main goal of this work is to make the data or information error free that is to be transmitted and also help the reader to understand the theory of RS codes and its encoding and decoding in order to make the errors detectable and correctable.
Keywords:
FPGA, Key Equation Solver (KES), Reed Solomon (RS), Syndrome Calculation (SC) and VHDL.
References:
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