Realization of BIST Architecture using SRAM Cell Based on Input Vector Monitoring
|International Journal of Electronics and Communication Engineering|
|© 2015 by SSRG - IJECE Journal|
|Volume 2 Issue 4|
|Year of Publication : 2015|
|Authors : Miruthubashini.S ,Venkatesan.K and Kirubakaran.T|
How to Cite?
Miruthubashini.S ,Venkatesan.K and Kirubakaran.T, "Realization of BIST Architecture using SRAM Cell Based on Input Vector Monitoring," SSRG International Journal of Electronics and Communication Engineering, vol. 2, no. 4, pp. 27-29, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I4P114
To perform testing during normal operation of the circuit, without forcing the circuit to go offline is concurrent BIST testing. Built-In Self Test (BIST) techniques constitute an attractive and practical solution, to solve the problem of testing VLSI circuits and systems. In this paper, we perform input vector monitoring BIST scheme, by monitoring a set of vectors called windows during its normal operation and the testing of the circuit is also carried on along with its normal operation of the circuit.
BIST, CUT, Concurrent, Input Vector Monitoring, Online BIST
 Almukhaizim S.,and Makris Y.,(2007)“Concurrent error detection methods for asynchronous burst mode machines,” IEEE Trans. Comput., vol. 56, no. 6, pp. 785–798.
 Almukhaizim S., Drineas P., and Makris Y.,(2006) “Entropy-driven parity tree selection for low-cost concurrent error detection,” IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol. 25, no. 8, pp. 1547–1554.
 Al-Asaad H., and Shringi M.,(2000) “On-Line Built-In Self-Test for Operational Faults,” Proc. of Conf. Systems Readiness Technology, pp.168-174.
 Abramovici M., Breuer M., and Friedman A.,( 1990.) “Digital Systems Testing and Testable Design,” Computer Science Press, New York.
 Bardell P. H., McAnney W.H., and Savir J., Built-In Test for VLSI: Pseudorandom Techniques. John Wiley & Sons, Inc, New York.
 Chandel R., and P. Daniel(2011) , "Concurrent Online Test Architecture for Multiple Controller Blocks with Minimum Fault Latency," Ninth IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops, pp.45-49, 26-28.
 Gizopoulos D., Halatsis C., Kranitis N., Paschalis A.,and Voyiatzis I.,(2005) “A concurrent BIST architecture based on a self testing RAM,” IEEE Trans. Rel., vol. 54, no. 1, pp. 69–78.
 Halatsis C., and Voyiatzis I.,(2005) “A low-cost concurrent BIST scheme for increased dependability,” IEEE Trans. Dependable Secure Comput.,vol. 2, no. 2, pp. 150–156.
 Huang L. R., Jou J. Y., and Kuo S. Y.,(1997) “Gauss-elimination based generation of multiple seed-polynomial pairs for LFSR,” IEEE Trans. Comput. Aided Design Integr.Circuits Syst., vol. 16, no. 9, pp. 1015–1024.
 Ivanov A., and Zorian Y.,(1992) “An effective BIST scheme for ROM’s,”IEEE Trans. Comput., vol. 41, no. 5, pp. 646–653.
 I. Voyiatzis, T. Haniotakis, C. Efstathiou, and H. Antonopoulou,(2010) “A concurrent BIST architecture based on monitoring square windows,” in Proc. 5th Int. Conf. DTIS, pp. 1–6.
 Kime C. R., Saluja K. K., and R. Sharma,(1988) “A concurrent testing technique for digital circuits,” IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol. 7, no. 12, pp. 1250–1260.
 Kime C. R., Saluja K. K., and R. Sharma.,(1986) “Concurrent comparative built-in testing of digital circuits,” Dept. Electr. Comput. Eng., Univ. Wisconsin, Madison, WI, USA, Tech. Rep. ECE-8711.
 Kochte M. A., Wunderlich H.-J., and C. Zoellin.,(2009) “Concurrent self-test with partially specified patterns for low test latency and overhead,” in Proc. 14th Eur. Test Symp., pp. 53–58.
 McCluskey E. J.,(1985) “Built-in self-test techniques,” IEEE Design Test Comput., vol. 2, no. 2, pp. 21–28.
 R. Sharma and K. K. Saluja, (1993)“Theory, analysis and implementation of an on-line BIST technique,” VLSI Design, vol. 1, no. 1, pp. 9–22.
 Rajski J., and Tyszer J.,(1993) “Test responses compaction in accumulators with rotate carry adders,” IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol. 12, no. 4, pp. 531–539.
 Stroud C.,( 2002) “A Designer’s Guide to Built-In Self-Test,” Kluwer Academic Publishers, Boston
 Voyiatzis I., (2008), “On reducing aliasing in accumulator-based compaction,”in Proc. Int. Conf. DTIS, pp. 1–12.
 Wolf W.,(2002) “Modern VLSI Design: System-on-Chip Design,” Prentice Hall, New Jersey.