Advancements in Semiconductor Assembly, Testing, and Packaging: A Global and Regional Perspective

International Journal of Electronics and Communication Engineering

© 2025 by SSRG - IJECE Journal

Volume 12 Issue 7

Year of Publication : 2025

Authors : Vy Thi Thanh Huong, Huu Q. Tran

10.14445/23488549/IJECE-V12I7P131

How to Cite?

Vy Thi Thanh Huong, Huu Q. Tran, "Advancements in Semiconductor Assembly, Testing, and Packaging: A Global and Regional Perspective," SSRG International Journal of Electronics and Communication Engineering, vol. 12,  no. 7, pp. 400-406, 2025. Crossref, https://doi.org/10.14445/23488549/IJECE-V12I7P131

Abstract:

The Assembly, Test, and Packaging (ATP) processes are pivotal in semiconductor manufacturing, ensuring chip reliability and performance for applications from consumer electronics to cutting-edge AI, 6G, and quantum computing systems. This review explores recent ATP advancements, including AI-driven automation, chiplet architectures, Fan-Out Wafer-Level Packaging (FOWLP), and sustainable practices using recyclable materials. It highlights innovative testing methods like adaptive testing and Built-In Self-Test (BIST), alongside emerging trends such as photonic interconnects and advanced thermal management. Key challenges-thermal management, scaling, supply chain resilience, and hardware security-are analyzed, with a special focus on Vietnam’s burgeoning role in the global semiconductor ecosystem. By integrating insights from AI-optimized assembly, eco-friendly packaging, and Vietnam’s supply chain dynamics, this survey underscores ATP’s critical role in next-generation electronics and advocates for innovation to address technological and regional challenges.

Keywords:

Artificial intelligence, Assembly, Test, Packaging, Semiconductor.

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