Full Custom Design and Implementation of 12-Bit Complex Multiplier

International Journal of Electronics and Communication Engineering

© 2025 by SSRG - IJECE Journal

Volume 12 Issue 8

Year of Publication : 2025

Authors : A. Lakshmi, P. Chandrasekhar Reddy, Esther Rani Thuraka

10.14445/23488549/IJECE-V12I8P104

How to Cite?

A. Lakshmi, P. Chandrasekhar Reddy, Esther Rani Thuraka, "Full Custom Design and Implementation of 12-Bit Complex Multiplier," SSRG International Journal of Electronics and Communication Engineering, vol. 12,  no. 8, pp. 40-50, 2025. Crossref, https://doi.org/10.14445/23488549/IJECE-V12I8P104

Abstract:

The complex multiplier is an important module used in co-processors, especially designed for signal processing in Graphical Processing Units (GPUs), Digital Signal Processors (DSPs), and certain Artificial Intelligence (AI) accelerators. These applications require a low area and low power. This work presents a novel strategy for complex number multiplication. The design is full custom and utilizes a circuit optimization technique. The complex multiplier is designed using the Bottom-up approach. It uses a radix-4 modified Booth encoder. These concepts are used for performance improvement. The process of multiplication is sped up as the radix-4 modified Booth encoder can decrease the rows of partial products to n/2, and carry-save adders are designed to add the partial products by using a smaller number of transistors to improve the speed of the addition process. Finally, an increase in speed, low power, and low area is achieved by the utilization of a smaller number of transistors overall. Hence, less silicon area is utilized. The design is implemented using Cadence tools for 12x12-bit signed and unsigned numbers and is simulated using ADE with Spectre simulator for both pre-layout and post-layout complex multiplier using 0.18μm technology. Novelty stems from its integrated approach of a new full-custom design strategy, meticulous circuit-level optimization, and the effective application of radix-4 Booth encoding to achieve a highly efficient 12-bit complex multiplier in terms of power, area, and speed.

Keywords:

Booth encoder, Circuit optimization, Complex multiplier, Full custom design, Low power, Silicon area.

References:

[1] Andrew D. Booth, “A Signed Binary Multiplication Technique,” The Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, no. 2, pp. 236-240, 1951.
[CrossRef] [Google Scholar] [Publisher Link]
[2] C.S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Transactions on Electronic Computers, vol. 13, no. 1, pp. 14-17, 1964.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Taewhan Kim, William Jao, and Steve Weng Kiang Tjiang, “Arithmetic Optimization using Carry Save Adders,” Proceedings of the 35th Annual Design Automation Conference, pp. 433-438, 1998.
[CrossRef] [Google Scholar] [Publisher Link]
[4] Jung-Yup Kang, and J.L. Gaudiot, “A Fast and Well-Structured Multiplier,” Euromicro Symposium on Digital System Design, Rennes, France, pp. 508-515, 2004.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Rizalafande Che Ismail, and Razaidi Hussin, “High Performance Complex Number Multiplier using Booth-Wallace Algorithm,” 2006 IEEE International Conference on Semiconductor Electronics, Kuala Lumpur, Malaysia, pp. 786-790, 2006.
[CrossRef] [Google Scholar] [Publisher Link]
[6] P.K. Saha, A. Banerjee, and A. Dandapat, “High Speed Low Power Complex Multiplier Design Using Parallel Adders and Subtractors,” International Journal on Electronic and Electrical Engineering, vol. 7, no. 11, pp. 38-46, 2009.
[Google Scholar]
[7] Monika Hemnani et al., “Hardware Optimization of Complex Multiplication Scheme for DSP Application,” 2015 International Conference on Computer, Communication and Control, Indore, India, pp. 1-4, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[8] K. Deergha Rao, Ch. Gangadhar, and Praveen K. Korrai, “FPGA Implementation of Complex Multiplier using Minimum Delay Vedic Real Multiplier Architecture,” 2016 IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering (UPCON), Varanasi, India, pp. 580-584, 2016.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Duy Manh Thi Nguyen et al., “Design and Implementation of Complex Multiplier with Low Power and High Speed,” 2021 15th International Conference on Advanced Computing and Applications (ACOMP), Ho Chi Minh City, Vietnam, pp. 215-219, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Ansha Noushad, and A.R. Abdul Rajak, “VLSI Implementation of Complex Multiplier using Vedic Mathematics and Study its Performance,” ARPN Journal of Engineering and Applied Sciences, vol. 16, no. 10, pp. 1058-1061, 2021. [Publisher Link]
[11] Mario Garrido et al., Hardware Architectures for the Fast Fourier Transform, Handbook of Signal Processing Systems, pp. 613-647, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Fahad Qureshi, Jarmo Takala, and Shuvra Bhattacharyya, Rotators in Fast Fourier Transforms, Embedded, Cyber-Physical, and IoT Systems, pp. 245-262, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[13] Carl Ingemarsson et al., “Efficient FPGA Mapping of Pipeline SDF FFT Cores,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2486-2497, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Jakub Žádník, and Jarmo Takala, “Low-Power Programmable Processor for Fast Fourier Transform based on Transport Triggered Architecture,” 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Brighton, UK, pp. 1423-1427, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[15] Shiann-Rong Kuang, Jian-Ping Wang, and Cang-Yuan Guo, “Modified Booth Multipliers with a Regular Partial Product Array,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp. 404-408, 2009.
[CrossRef] [Google Scholar] [Publisher Link]
[16] Ravindra P. Rajput, and M.N. Shanmukha Swamy, “High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers,” 2012 UKSim 14th International Conference on Computer Modelling and Simulation, Cambridge, UK, pp. 649-654, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[17] Amir Fathi et al., “Low Latency, Glitch-Free Booth Encoder-Decoder for High-Speed Multipliers,” IEICE Electronics Express, vol. 9, no. 16, pp. 1335-1341, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Amir Fathi et al., “Ultra High Speed Modified Booth Encoding Architecture for High-Speed Parallel Accumulations,” IEICE Transactions on Electronics, vol. 95, no. 4, pp. 706-709, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[19] Venkata Krishna Odugu, C. Venkata Narasimhulu, and K. Satya Prasad, “Design and Implementation of Low Complexity Circular Symmetric 2D FIR Filter Architectures,” Multidimensional Systems and Signal Processing, vol. 31, pp. 1385-1410, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[20] Zahra Ebrahimi et al., “Rapid: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 3, pp. 712-725, 2023.
[CrossRef] [Google Scholar] [Publisher Link]
[21] Aloke Saha et al., “Novel CMOS Multi-Bit Counter for Speed-Power Optimization in Multiplier Design,” AEU - International Journal of Electronics and Communications, vol. 95, pp. 189-198, 2018.
[CrossRef] [Google Scholar] [Publisher Link]
[22] Lakshmanan, M. Othman, and M.A.M. Ali, “High Performance Parallel Multiplier Using Wallace-Booth Algorithm,” Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age, Penang, Malaysia, pp. 433-436, 2002.
[CrossRef] [Google Scholar] [Publisher Link]
[23] S.M. Sait, A.A. Farooqui, and G.F. Beckhoff, “A Novel Technique for Fast Multiplication,” Proceedings International Phoenix Conference on Computers and Communications, USA, pp. 109-114, 1995.
[CrossRef] [Google Scholar] [Publisher Link]
[24] B.P.R. Che Ismail et al., “Performance Enhancement and Reduced Area Parallel Multiplier,” IEEE National Symposium on Microelectronics, pp. 252-258, 2005.
[Google Scholar]